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FPGA-based implementation of different families of fractional-order chaotic oscillators applying Grunwald-Letnikov method

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COMMUNICATIONS IN NONLINEAR SCIENCE AND NUMERICAL SIMULATION 2019年第Jun.期72卷 516-527页

作者： Dalia Pano-Azucena, Ana Ovilla-Martinez, Brisbane Tlelo-Cuautle, Esteban Manuel Munoz-Pacheco, Jesus Gerardo de la Fraga, Luis INAOE Dept Elect Puebla 72840 Mexico Univ Autonoma Metropolitana Unidad Iztapalapa Mexico City 09340 DF Mexico BUAP Fac Elect Sci Puebla 72570 Mexico CINVESTAV Comp Sci Dept Mexico City 07360 DF Mexico

Fractional-order chaotic oscillators are a hot topic of research and nowadays many new mathematical models have been introduced, which can be suitable for the development of novel applications in all related fields of science and engineering. However, the challenge is their implementation that can be performed using electronic devices. In this manner, we highlight the implementation of different families of fractional-order chaotic oscillators using field-programmable gate arrays (FPGAs). We detail the hardware implementation when solving the mathematical models applying the Grunwald-Letnikov method, and highlight the short-memory principle, which memory length is designed using specialized random-access-memory and read-only-memory blocks. In addition, we show how to reduce hardware resources by reusing blocks that are controlled by an especial architecture that is introduced herein, in order to perform an efficient processing of the data. Finally, using Cyclone IV GX FPGA DE2i-150 from Altera, DAS1612 digital-to-analog converter and fixed-point arithmetic of 32 bits, we provide experimental results that were observed in a Lecroy's oscilloscope showing working frequencies of fractional-order chaotic attractors between 77.59 and 84.9 MHz. (C) 2019 Elsevier B.V. All rights reserved.

关键词： Fractional-order chaotic oscillator field-programmable gate array Grunwald-Letnikov method Fixed-point arithmetic

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Parallelism Optimized Architecture on FPGA for Real-Time Traffic Light Detection

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IEEE ACCESS 2019年 7卷 178167-178176页

作者： Wu, Xue-Hua Hu, Renjie Bao, Yu-Qing Southeast Univ Sch Elect Engn Nanjing 210096 Peoples R China Nanjing Normal Univ Sch Elect & Automat Engn Nanjing 210023 Peoples R China

In this paper, a portable assistance system is designed to help the visually impaired to detect the traffic light. The designed system is realized on the basis of the AdaBoost algorithm, which is fast and robust in object detections. In order to accelerate the AdaBoost-based approach, a flexible parallel architecture is implemented on the field-programmable gate array (FPGA) platform. The architecture is designed utilizing the parallelism of computations in the AdaBoost-based detection. The computations of the window integral image are implemented in parallel, and the confidences of the weak classifiers are calculated in parallel. The parameters of the weak classifiers are trained by the AdaBoost algorithm with multi-layer features in the MATLAB software, and then are configured on the FPGA platform via the Vivado design suite before the detection process. The parallelism optimized architecture is implemented on an Artix-7 FPGA at 200 MHZ. Experiments show that it can detect the traffic light in videos with a rate of 30 frames per second (fps).

关键词： AdaBoost algorithm field-programmable gate array integral image parallel architecture traffic light detection

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A Hardware-Oriented Algorithm for Ultra-High-Speed Object Detection

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IEEE SENSORS JOURNAL 2019年第10期19卷 3818-3831页

作者： Li, Jianquan Liu, Xilong Liu, Fangfang Xu, De Gu, Qingyi Ishii, Idaku Chinese Acad Sci Res Ctr Precis Sensing & Control Inst Automat Beijing 100190 Peoples R China Univ Chinese Acad Sci Sch Comp & Control Engn Beijing 101408 Peoples R China Hiroshima Univ Dept Syst Cybernet Robot Lab Hiroshima 7398527 Japan

This paper describes a novel hardware-oriented algorithm that can be implemented on a field-programmable gate array in a high-speed vision platform for detection of multiple objects with clear texture information in images of 512 x 512 pixels at 10000 frames per second (fps) under complex background. The proposed algorithm is specially designed for devices with limited hardware resource for high-frame-rate, high-data-throughput, and high-parallelism processing of video streams with low latency. The proposed algorithm is based on the conventional histograms of oriented gradient (HOC) descriptor and support vector machine classifier algorithms. Considering the trade-off between speed and accuracy, many hardware-based optimization operations were implemented. The data throughput is nearly 29.30 Gbps while the latency for feature extraction is 0.76 us (61 clock period). After hardware-based image processing, the source image and the detected object features can be transferred to a personal computer for recording or post-processing at 10000 fps. Several experiments were done to demonstrate the performance of our proposed algorithm for ultra-high-speed moving object detection with clear texture information in images.

关键词： Hardware implementation high-frame-rate vision field-programmable gate array multi-object detection histograms of oriented gradient support vector machine

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A hardware/software architecture dedicated to model predictive control law and implemented into an FPGA platform

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INTERNATIONAL JOURNAL OF AUTOMATION AND CONTROL 2019年第3期13卷 301-323页

作者： Sirine, Telmoudi Brini Badreddine, Bouzouita Faouzi, Bouani Turns El Manar Univ Natl Engn Sch Tunis ENIT LR11ES20 Lab Anal Concept & Control Syst Tunis Tunisia Univ Sousse Natl Engn Sch Sousse Sousse Tunisia

Model predictive control (MPC) is an optimisation-based strategy for high-performance control engineering practice and real-time applications. This method needs to solve online a quadratic programming (QP) problem at each sample time to find optimal control sequence. In this paper, a new optimised MPC architecture is presented, for a gradient-based QP solver to implement linear MPC on a field-programmable gate array platform, which allows obtaining high-quality performances for the real-time control applications. It requires a manual programming of the high-level C/C ++ code in opposition to the other presented approaches, which automatically generates the code. The efficiency of this approach is completed with real time control of the water level of a single tank system running on a Nanoboard 3000XN chip using a conception environment (Altium Designer), while comparing between the MPC and PID controllers.

关键词： field-programmable gate array FPGA predictive control quadratic optimisation problem PID controller Altium designer model predictive control MPC

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CNN Acceleration With Hardware-Efficient Dataflow for Super-Resolution

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IEEE ACCESS 2020年 8卷 187754-187765页

作者： Lee, Sumin Joo, Sunghwan Ahn, Hong Keun Jung, Seong-Ook Yonsei Univ Sch Elect & Elect Engn Seoul 03722 South Korea

The convolutional neural network (CNN)-based super-resolution (SR) has shown outstanding performance in the field of computer vision. The implementation of inference hardware for CNN-based SR has suffered from the intensive computation with severely unbalanced computation load among layers. Various light-weighted SR networks have been researched with little performance degradation. However, the hardware-efficient dataflow is also required to efficiently accelerate inference hardware within limited resources. In this article, we propose the hardware-efficient dataflow of CNN-based SR that reduces computation load by increasing data reuse and increases process element (PE) utilization by balancing the computation load among layers for high throughput. In the proposed dataflow, row-wise pixels in the receptive field are computed by circularly shifting memory addresses to maximize data reuse. The partial convolution is exploited in a layer-based pipeline architecture to relieve intensive computation in a single pipeline stage. The delay-balancing with adjusting parallelism is employed for balancing computations precisely in the overall layers. Furthermore, the inference hardware of CNN-based SR is implemented for 4K ultrahigh definition at 60 fps on a field-programmable gate array (FPGA). For hardware-friendly computation, the quantization of activation and weight is adopted. The proposed hardware shows an average peak signal-to-noise ratio of 36.42 dB in the Set-5 dataset with a memory usage of 53 KB and an average PE utilization of 76.7% in the overall layers. Thus, it achieves the lowest memory usage and highest PE utilization compared with other inference hardware for CNN-based SR.

关键词： Convolutional neural network dataflow field-programmable gate array inference hardware 4K ultrahigh definition process element utilization super-resolution

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FPGA Implementation of Hardware-Oriented Chaotic Boltzmann Machines

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IEEE ACCESS 2020年 8卷 204360-204377页

作者： Kawashima, Ichiro Morie, Takashi Tamukoh, Hakaru Kyushu Inst Technol Grad Sch Life Sci & Syst Engn Kitakyushu Fukuoka 8080196 Japan

Boltzmann machines (BMs) are useful in various applications but are limited by their requirement to generate random numbers. In contrast, chaotic Boltzmann machines (CBMs) are neural networks that imitate the stochastic behavior of BMs with the chaotic dynamics and deterministic behavior, without random numbers. CBMs can potentially require fewer hardware resources than the original algorithms due to the unnecessity of random number generators. In this study, hardware-oriented algorithms and a differential multiply-accumulation operation are proposed to overcome the difficulties of implementing CBMs on field-programmable gate arrays (FPGAs). A hardware-oriented algorithm for CBMs, which includes fixed-point operations and shift operations, is proposed to reduce hardware resource utilization in the implemented circuits. In particular, the differential multiply-accumulate operation allows us to implement the multiply-accumulate operation with block random access memory and digital signal processors to reduce the consumption of lookup tables and flip-flops in FPGAs without losing the calculation speed. Our proposed approach was evaluated in numerical simulations, logical synthesis, and FPGA implementation. The calculation speed of FPGA-implemented CBMs was compared with software-implemented CBMs, which resulted in 1 / 6,500 of calculation time reduction in a 300-neuron CBM. Moreover, 2,048 neurons of CBM were realized by the logical synthesis. Therefore, the proposed hardware implementation of CBMs was shown to be feasible. The proposed CBMs can solve combinatorial optimization problems at a larger scale with fewer resources.

关键词： Chaotic Boltzmann machines combinatorial optimization problems Ising model field-programmable gate array

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Design of an Ethernet-VLC adapter based on FPGA

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JOURNAL OF COMPUTATIONAL METHODS IN SCIENCES AND ENGINEERING 2019年第3期19卷 779-787页

作者： Ye, X. Sun, G. Zhao, W. Wang, R. Nankai Univ Coll Elect Informat & Opt Engn Tianjin Peoples R China

A design of Ethernet adapter for visible light communication (VLC) is proposed in this paper. Based on field-programmable gate array (FPGA) technology and Ethernet protocols, the design applies Ethernet to VLC channel, enabling two-way transmission between both channels, giving solution to the conversion of signal between different coding formats. 8B10B DC-balanced encoding/decoding is used for VLC transceivers to ensure reliable and stable communication. At 1000BASE-T duplex mode, the maximum real-time net data rate on the VLC channel is 300Mbps by sending and receiving Ethernet frames in point-to-point communication with optical transceivers using phosphorescent white light emitting diode (WLED).

关键词： Visible light communication Ethernet field-programmable gate array white light emitting diode

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Rethinking arithmetic for deep neural networks

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PHILOSOPHICAL TRANSACTIONS OF THE ROYAL SOCIETY A-MATHEMATICAL PHYSICAL AND ENGINEERING SCIENCES 2020年第2166期378卷 20190051-20190051页

作者： Constantinides, G. A. Imperial Coll London EEE Dept London England

We consider efficiency in the implementation of deep neural networks. Hardware accelerators are gaining interest as machine learning becomes one of the drivers of high-performance computing. In these accelerators, the directed graph describing a neural network can be implemented as a directed graph describing a Boolean circuit. We make this observation precise, leading naturally to an understanding of practical neural networks as discrete functions, and show that the so-called binarized neural networks are functionally complete. In general, our results suggest that it is valuable to consider Boolean circuits as neural networks, leading to the question of which circuit topologies are promising. We argue that continuity is central to generalization in learning, explore the interaction between data coding, network topology, and node functionality for continuity and pose some open questions for future research. As a first step to bridging the gap between continuous and Boolean views of neural network accelerators, we present some recent results from our work on LUTNet, a novel field-programmable gate array inference approach. Finally, we conclude with additional possible fruitful avenues for research bridging the continuous and discrete views of neural networks. This article is part of a discussion meeting issue 'Numerical algorithms for high-performance computational science'.

关键词： neural network computing accelerator field-programmable gate array

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76-2: Scalable Real-time Holography Processor Architecture

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SID Symposium Digest of Technical Papers 2023年第1期54卷

作者： Wonok Kwon Sanghoon Cheon Joongki Park Digital Holography Research Section Electronics and Telecommunications Research Institute

In this paper, we present a fast and efficient scalable holographic video processor using a layer-based method, which employs a modified inverse Fresnel transform. To verify the performance of the proposed architecture, we design a single-layered holography core using a fixed-point model and test its performance on a field-programmable gate array. The implemented real-time hologram processor features a 1k × 1k size fast Fourier transform and a 30 frames/sec conversion rate in 4K color spatial light modulators after applying 2× linear interpolation. All real-time images on computer screens, such as YouTube and movies, are converted into holograms within 22 ms.

关键词： Hologram Real-time holography processor Computer-generated hologram field-programmable gate array

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Conventional and machine learning approaches as countermeasures against hardware trojan attacks

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MICROPROCESSORS AND MICROSYSTEMS 2020年 79卷 103295-103295页

作者： Liakos, Konstantinos G. Georgakilas, Georgios K. Moustakidis, Serafeim Sklavos, Nicolas Plessas, Fotis C. Univ Thessaly Sch Engn Dept Elect & Comp Engn CAS Lab Grp Volos Hellas Greece AIDEAS Tallinn Estonia Univ Patras Dept Comp Engn & Informat Patras Hellas Greece

Every year, the rate at which technology is applied on areas of our everyday life is increasing at a steady pace. This rapid development drives the technology companies to design and fabricate their integrated circuits (ICs) in non-trustworthy outsourcing foundries to reduce the cost, thus, leaving space for a synchronous form of virus, known as Hardware Trojan (HT), to be developed. HTs leak encrypted information, degrade device performance or lead to total destruction. To reduce the risks associated with these viruses, various approaches have been developed aiming to prevent and detect them, based on conventional or machine learning methods. Ideally, any undesired modification made to an IC should be detectable by pre-silicon verification/simulation and post-silicon testing. The infected circuit can be inserted in different stages of the manufacturing process, rendering the detection of HTs a complicated procedure. In this paper, we present a comprehensive review of research dedicated to countermeasures against HTs embedded into ICs. The literature is grouped in four main categories;(a) conventional HT detection approaches, (b) machine learning for HT countermeasures, (c) design for security and (d) runtime monitor.

关键词： Hardware security Hardware trojans Integrated circuits Application-specific integrated circuit field-programmable gate array Artificial intelligence Machine learning Detection Prevention Facilitation Design for security Runtime monitor Literature review

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