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Remote web-based control laboratories using embedded Linux and field-programmable gate array

PROCEEDINGS OF THE INSTITUTION OF MECHANICAL ENGINEERS PART I-JOURNAL OF SYSTEMS AND CONTROL ENGINEERING 2018年第9期232卷 1146-1154页

作者： Jaziri, Ibtihel Charaabi, Lotfi Jelassi, Khaled Univ Tunis El Manar Ecole Natl Ingn Tunis Lab Syst Elect LR11ES15 Tunis 1002 Tunisia

In this article, the authors present a new approach based on the hardware and software architecture using embedded Linux and field-programmable gate array for implementation of remote laboratories. It combines a set of software and hardware resources in the interest of offering a multidisciplinary low-cost open platform for engineering education. Thus, the proposed approach allows students to develop low-cost and easily programmable prototypes of electrical systems control, robotics, and other embedded devices that feature Internet connectivity, Input/output, networking, and operating systems. In the proposed work, the authors present a codesign solution with flexible hardware devices, providing characteristics of multipurpose use with many experimental devices, and fully configurable graphical user interface. The physical setup and communication principles of hardware architecture are based on two types of devices: the Beaglebone running embedded Linux operating system and the field-programmable logic gate array. The graphical user interface is designed as a web page based on HTML and PHP programming languages;this allows the teachers/students to control the system easily, parameterize, and observe the behavior of the controller/system remotely.

关键词： Remote laboratory control education embedded Linux field-programmable gate array embedded web server

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NIWAS: A non-interactive watermark authentication scheme for industrial field-programmable gate array designs

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ADVANCES IN MECHANICAL ENGINEERING 2018年第6期10卷

作者： Long, Jing Zhang, Dafang Liang, Wei Ning, Zuoting Zhang, Qingyong Hunan Univ Coll Comp Sci & Elect Engn Changsha 410082 Hunan Peoples R China Xiamen Univ Technol Sch Optoelect & Commun Engn Xiamen Peoples R China Hunan Police Acad Hunan Prov Key Lab Network Invest Technol Changsha Hunan Peoples R China Fujian Univ Technol Sch Mech & Automot Engn Fuzhou Fujian Peoples R China

Except the network attacks, the industrial networked devices in Internet of things are also threatened by intellectual property infringement. Watermarking technique is a prevalent way to avoid this threat. Previous work on authenticating a watermark in industrial intellectual properties easily discloses sensitive information of real embedded watermarks. In this case, the evidence of identifying the ownership of industrial intellectual property may be attacked by the illegal verifiers. Although several watermark detection techniques can address the disclosure of sensitive information in detection procedure, the efficiency of detection is relatively low. Besides, it may yield large communication overhead of multiple authentication rounds. Motivated by the needs of robustness and efficiency, this work proposed a zero-knowledge approach to authenticate ownership of field-programmable gate array intellectual property design in industrial environment, named NIWAS. The prover can convince the verifier that he knows a secret in the suspected intellectual property design via only one interaction. Real locations of watermarks are concealed through location obfuscation. With the received authentication package from the prover, the verifier cannot obtain other useful information about the watermarks. The experiments show that NIWAS achieves high efficiency and robustness of watermark detection.

关键词： Intellectual property Internet of things field-programmable gate array zero-knowledge robustness

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Full image-processing pipeline in field-programmable gate array for a small endoscopic camera

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JOURNAL OF ELECTRONIC IMAGING 2017年第1期26卷 013005-013005页

作者： Mostafa, Sheikh Shanawaz Natercia Sousa, L. Ferreira, Nuno Fabio Sousa, Ricardo M. Santos, Joao Wany, Martin Morgado-Dias, F. Univ Lisbon Inst Super Tecn Ave Rovisco Pais 1 P-1049001 Lisbon Portugal Madeira Interact Technol Inst Polo Cient & Tecnol Madeira Floor 2 P-9020105 Funchal Portugal Univ Madeira Colegio Jesuitas Praca MunicipioRua Ferreiros P-9000082 Funchal Portugal AWAIBA CMOSIS PORTUGAL Madeira Tecnopolo P-9020105 Funchal Portugal

Endoscopy is an imaging procedure used for diagnosis as well as for some surgical purposes. The camera used for the endoscopy should be small and able to produce a good quality image or video, to reduce discomfort of the patients, and to increase the efficiency of the medical team. To achieve these fundamental goals, a small endoscopy camera with a footprint of 1 mm x 1 mm x 1.65 mm is used. Due to the physical properties of the sensors and human vision system limitations, different image-processing algorithms, such as noise reduction, demosaicking, and gamma correction, among others, are needed to faithfully reproduce the image or video. A full image-processing pipeline is implemented using a field-programmable gate array (FPGA) to accomplish a high frame rate of 60 fps with minimum processing delay. Along with this, a viewer has also been developed to display and control the image-processing pipeline. The control and data transfer are done by a USB 3.0 end point in the computer. The full developed system achieves real-time processing of the image and fits in a Xilinx Spartan-6LX150 FPGA. (C) 2017 SPIE and IS&T

关键词： endoscopic camera image processing field-programmable gate array high frame rate

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Modified artificial bee colony optimisation based FIR filter design with experimental validation using field-programmable gate array

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IET SIGNAL PROCESSING 2016年第8期10卷 955-964页

作者： Dwivedi, Atul Kumar Ghosh, Subhojit Londhe, Narendra D. NIT Raipur Dept Elect Engn Raipur Madhya Pradesh India

Optimisation based design of finite impulse response (FIR) filters has been an active area of research for quite some time. The various algorithms proposed for FIR filter design aim at meeting a set of desired specifications in the frequency domain. Evolutionary algorithms have been found to be very effective for FIR filter design because of the non-linear, non-differentiable and non-convex nature of the associated optimisation problem. The present work proposes two modified versions of a recently developed evolutionary technique i.e. artificial bee colony (ABC) algorithm for design of FIR filters. The applicability of the proposed approach has been evaluated by comparing its response with conventional reported filter design techniques. The proposed variants of ABC are found to outperform other non-convex algorithms in achieving the desired specifications. In addition to the simulation results, the designed filters have been implemented in hardware using Xilinx-xc7vx330t-3ffg1157 (Virtex-7) field programmable gate array. The hardware implementation allows validation of the proposed techniques for practical filtering applications by considering real time operation parameters.

关键词： FIR filters evolutionary computation modified artificial bee colony optimisation based FIR filter design field-programmable gate array finite impulse response filters frequency domain evolutionary algorithms real time operation parameters Xilinx-xc7vx330t-3ffg1157 FPGA

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Low power 2D finite impulse response filter design using modified artificial bee colony algorithm with experimental validation using field-programmable gate array

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IET SCIENCE MEASUREMENT & TECHNOLOGY 2016年第6期10卷 671-678页

作者： Dwivedi, Atul Kumar Ghosh, Subhojit Londhe, Narendra D. NIT Raipur Dept Elect Engn Raipur Madhya Pradesh India

Motivated by the need of reducing power consumption (PC) in two dimensional (2D) finite impulse response (FIR) filters, in this work, the 2D FIR filter design task is formulated as an optimisation problem that seeks to attain the desired frequency response and reduces PC. The optimisation problem has been solved using the modified version of artificial bee colony algorithm. The applicability of the proposed approach has been evaluated by designing circular shaped 2D FIR filters for a set of specifications in frequency domain. The designed filters have been compared with other reported state of the art techniques. The evaluation is carried out in terms of pass band and stop band ripple minimisation, convergence profile and PC during filter execution in hardware. The proposed technique is found to outperform all other techniques in achieving minimum ripple for a given filter order. To prove the effectiveness of the proposed approach for PC reduction, the designed filters have been implemented in hardware using field-programmable gate array (xc7vx485t-2ffg1761). The PC computed using Xilinx X-power analyser shows that 23.53% power can be saved using the proposed approach as compared with conventional design approaches.

关键词： FIR filters field programmable gate arrays singular value decomposition band-pass filters band-stop filters minimisation low power 2D finite impulse response filter design modified artificial bee colony algorithm field-programmable gate array cooling maintenance power consumption PC low power two-dimensional FIR filter singular value decomposition Hamming distance optimisation problem circular shaped 2D FIR filter frequency domain analysis pass band ripple minimisation stop band ripple minimisation Xilinx X-power analyser

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A 16-NM MULTIPROCESSING SYSTEM-ON-CHIP field-programmable gate array PLATFORM

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IEEE MICRO 2016年第2期36卷 48-62页

作者： Ahmad, Sagheer Boppana, Vamsi Ganusov, Ilya Kathail, Vinod Rajagopalan, Vidya Wittig, Ralph Xilinx SoC Bangalore Karnataka India Xilinx Bangalore Karnataka India Xilinx Proc Syst Software & Applicat Engn Bangalore Karnataka India Xilinx Comp Platforms Bangalore Karnataka India

THE ZYNQ ULTRASCALE+ MPSOC INCREASES PERFORMANCE AND POWER EFFICIENCY, ADDS SYSTEM-WIDE COHERENCY AND SHARED VIRTUAL MEMORY BETWEEN THE SOC AND THE field-programmable gate array (FPGA), AND RAISES THE PROGRAMMING ABSTRACTION BY INTRODUCING A HETEROGENEOUS, SYSTEM-WIDE COMPILER. THE SDSOC ENVIRONMENT COMBINES THE ARM COMPILER WITH A HIGH-LEVEL SYNTHESIS TECHNOLOGY-BASED FPGA COMPILER AND A FULL-SYSTEM OPTIMIZING COMPILER TO TARGET ALL ELEMENTS OF THE HETEROGENEOUS SOC FROM A COMMON PROGRAM SOURCE.

关键词： field programmable gate arrays field-programmable gate array Memory management Microprocessors multiprocessor Random access memory Real-time systems Streaming media system on chip Zynq

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Flexible tunable optical transceiver based on field-programmable gate array for time and wavelength-division multiplexed passive optical network systems

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OPTICAL ENGINEERING 2016年第8期55卷 086110-1-086110-7页

作者： Hu, Sheng Yu, Yonglin Li, Cheng Zhu, Yao Han, Yu Huazhong Univ Sci & Technol Wuhan Natl Lab Optoelect Sch Opt & Elect Informat Luoyu Rd 1037 Wuhan 430074 Peoples R China Wuhan Huagong Genuine Opt Tech Co Ltd HG Genuine HUST Sci & Tech Pk Wuhan 430073 Peoples R China

Time-and wavelength-division multiplexed passive optical networks (TWDM-PONs) have been selected by the full services access network community as the most suitable technology for next-generation optical access networks. A key technology in TWDM-PON is the colorless optical network unit transceiver. This paper proposes a flexible, tunable optical transceiver that uses directly modulated tunable lasers. Using a field-programmable gate array (FPGA), programmable reconfigurations and testing capabilities can be embedded into the transceiver in order to implement wavelength control, signal generation, pre-emphasis for upstream, and a bit error rate (BER) test for the downstream. To ensure high-quality signal generation at different bitrates, impedance matching between the laser driver circuit and the laser diodes is optimized. Using the proposed transceiver, three-section-distributed Bragg reflector tunable lasers at or below 2.5 Gb/s direct modulation through a 40-km standard mode fiber transmission were successfully implemented. (C) 2016 Society of Photo-Optical Instrumentation Engineers (SPIE)

关键词： tunable transceiver colorless optical network unit field-programmable gate array time-and wavelength-division multiplexed passive optical network

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Exploration of preprocessing architectures for field-programmable gate array-based thermal-visual smart camera

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JOURNAL OF ELECTRONIC IMAGING 2016年第4期25卷 041006-041006页

作者： Imran, Muhammad Rinner, Bernhard Zand, Sajjad Zandi O'Nils, Mattias Mid Sweden Univ Dept Elect Design Holmgatan 10 S-85170 Sundsvall Sweden Alpen Adria Univ Inst Networked & Embedded Syst Lakeside Pk B02b A-9020 Klagenfurt Austria

Embedded smart cameras are gaining in popularity for a number of real-time outdoor surveillance applications. However, there are still challenges, i.e., computational latency, variation in illumination, and occlusion. To solve these challenges, multimodal systems, integrating multiple imagers can be utilized. However, trade-off is more stringent requirements on processing and communication for embedded platforms. To meet these challenges, we investigated two low-complexity and high-performance preprocessing architectures for a multiple imagers' node on a field-programmable gate array (FPGA). In the proposed architectures, majority of the tasks are performed on the thermal images because of the lower spatial resolution. Analysis with different sets of images show that the system with proposed architectures offers better detection performance and can reduce output data from 1.7 to 99 times as compared with full-size images. The proposed architectures can achieve a frame rate of 53 fps, logics utilization from 2.1% to 4.1%, memory consumption 987 to 148 KB and power consumption in the range of 141 to 163 mW on Artix-7 FPGA. This concludes that the proposed architectures offer reduced design complexity and lower processing and communication requirements while retaining the configurability of the system. (C) 2016 SPIE and IS&T.

关键词： smart camera preprocessing architecture thermal field-programmable gate array

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Efficient field-programmable gate array implementation of CCSDS 121.0-B-2 lossless data compression algorithm for image compression

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JOURNAL OF APPLIED REMOTE SENSING 2015年第1期9卷 097499-1-097499-15页

作者： Kranitis, Nektarios Sideris, Ioannis Tsigkanos, Antonios Theodorou, Georgios Paschalis, Antonios Vitulli, Raffaele Univ Athens Dept Informat & Telecommun Digital Syst & Comp Architecture Lab Athens 15784 Greece European Space Agcy NL-2201 AZ Noordwijk Netherlands

The Consultative Committee for Space Data Systems (CCSDS) 121.0-B-2 lossless data compression standard defines a lossless adaptive source coding algorithm which is applicable to a wide range of imaging and nonimaging data. We introduce a field-programmable gate array (FPGA) implementation of CCSDS 121.0-B-2 as an intellectual property (IP) core with the following features: (a) it is enhanced with a two-dimensional (2-D) second-order predictor making it more suitable for image compression, (b) it is enhanced with near-lossless compression functionality, (c) its parallel, pipelined architecture provides high data-rate performance with a maximum achievable throughput of 205 Msamples/s (3.2 Gbps at 16 bit) when targeting the Xilinx Virtex-5QV FPGA, and (d) it requires very low FPGA resources. When mission requirements impose lossless image compression, the CCSDS 121.0-B-2 IP core provides a very low implementation cost solution. According to European Space Agency PROBA-3 Bridging Phase, the CCSDS 121.0-B-2 IP core will be implemented in a Microsemi RTAX2000 FPGA, hosted in the data processing unit of the Coronagraph Control Box, of the Association of Spacecraft for Polarimetric and Imaging Investigation of the Corona of the Sun Coronagraph System Payload. To the best of our knowledge, it is the fastest FPGA implementation of CCSDS 121.0-B-2 to date, also including a 2-D second-order predictor making it more suitable for image compression. (C) 2015 Society of Photo-Optical Instrumentation Engineers (SPIE)

关键词： lossless data compression image compression Consultative Committee for Space Data Systems on-board payload data processing field-programmable gate array

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Permanent magnet synchronous machines flux linkage estimation with zero steady-state error and its field-programmable gate array implementation

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IET ELECTRIC POWER APPLICATIONS 2015年第4期9卷 332-343页

作者： Zanuso, Giovanni Peretti, Luca Zigliotto, Mauro ABB Corp Res Dept Elect Syst S-72178 Vasteras Sweden Univ Padua Dept Tech & Management Ind Syst I-36100 Vicenza Italy

The paper analyses a combined current model-voltage model estimator for flux linkages in permanent magnet synchronous machines, with the capability of converging to exact flux estimation even in presence of mismatches because of magnetic saturation. As a trend in next-generation electric drives, the whole algorithm, including both the flux estimator and the standard field-oriented control, has been implemented in a field-programmable gate array (FPGA) chip. Simulations and experimental tests, along with some figures for the FPGA selection, have been included in the study.

关键词： permanent magnet machines synchronous machines field programmable gate arrays electric drives digital control machine vector control permanent magnet synchronous machines flux linkage estimation zero steady-state error field-programmable gate array combined current model-voltage model estimator magnetic saturation next-generation electric drives standard field-oriented control FPGA chip

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