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A TIME-DOMAIN PULSE AMPLITUDE AND WIDTH DISCRIMINATION METHOD FOR PHOTON COUNTING

METROLOGY AND MEASUREMENT SYSTEMS 2018年第2期25卷 269-282页

作者： del Mar Correa, Maryam Perez, Freddy R. Univ Pondficia Bolivariana Ctr Ciencia Basica Grp Opt & Espect Circular 1 70-01 Medellin Colombia

This work shows a time-domain method for the discrimination and digitization of parameters of voltage pulses coming from optical detectors, taking into account the presence of electronic noise and afterpulsing. Our scheme is based on an FPGA-based time-to-digital converter as well as an adjustable-threshold comparator complemented with commercial elements. Here, the design, implementation and optimization of a multiphase TDC using delay lines shorter than a single clock period is also described. The performance of this signal processing system is discussed through the results from the statistical code density test, statistical distributions of measurements and information gathered from an optical detector. Unlike dual voltage threshold discriminators or constant-fraction discriminators, the proposed method uses amplitude and time information to define an adjustable discrimination window that enables the acquisition of spectra.

关键词： field-programmable gate array time-to-digital converter spectroscopy photomultiplier photon counting discriminator after-pulsing low-voltage differential signalling

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Survey on hardware implementation of random number generators on FPGA: Theory and experimental analyses

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COMPUTER SCIENCE REVIEW 2018年第Feb.期27卷 135-153页

作者： Bakiri, Mohammed Guyeux, Christophe Couchot, Jean-Francois Oudjida, Abdelkrim Kamel Univ Bourgogne Franche Comte UMR CNRS 6174 DISC Dept Femto ST Inst F-90010 Belfort France Ctr Dev Technol Avancees ASM DMN Dept Cite 20 Aout 1956 Baba HassenBP 17 Algiers 16303 Algeria

Random number generation refers to many applications such as simulation, numerical analysis, cryptography etc. field programmable gate array (FPGA) are reconfigurable hardware systems, which allow rapid prototyping. This research work is the first comprehensive survey on how random number generators are implemented on field programmable gate arrays (FPGAs). A rich and up-to-date list of generators specifically mapped to FPGA are presented with deep technical details on their definitions and implementations. A classification of these generators is presented, which encompasses linear and nonlinear (chaotic) pseudo and truly random number generators. A statistical comparison through standard batteries of tests, as well as implementation comparison based on speed and area performances, are finally presented. (C) 2018 Elsevier Inc. All rights reserved.

关键词： Random number generators field-programmable gate array Chaos Physical security Hardware Security Applied cryptography

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Optimizing FPGA-based CNN accelerator for energy efficiency with an extended Roofline model

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TURKISH JOURNAL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCES 2018年第2期26卷 919-935页

作者： Ayat, Sayed Omid Khalil-Hani, Mohamed Ab Rahman, Ab Al-Hadi Univ Teknol Malaysia Fac Elect Engn VeCAD Res Lab Skudai Johor Malaysia

In recent years, the convolutional neural network (CNN) has found wide acceptance in solving practical computer vision and image recognition problems. Also recently, due to its flexibility, faster development time, and energy efficiency, the field-programmable gate array (FPGA) has become an attractive solution to exploit the inherent parallelism in the feedforward process of the CNN. However, to meet the demands for high accuracy of today's practical recognition applications that typically have massive datasets, the sizes of CNNs have to be larger and deeper. Enlargement of the CNN aggravates the problem of off-chip memory bottleneck in the FPGA platform since there is not enough space to save large datasets on-chip. In this work, we propose a memory system architecture that best matches the off-chip memory traffic with the optimum throughput of the computation engine, while it operates at the maximum allowable frequency. With the help of an extended version of the Roofline model proposed in this work, we can estimate memory bandwidth utilization of the system at different operating frequencies since the proposed model considers operating frequency in addition to bandwidth utilization and throughput. In order to find the optimal solution that has the best energy efficiency, we make a trade-off between energy efficiency and computational throughput. This solution saves 18% of energy utilization with the trade-off having less than 2% reduction in throughput performance. We also propose to use a race-to-halt strategy to further improve the energy efficiency of the designed CNN accelerator. Experimental results show that our CNN accelerator can achieve a peak performance of 52.11 GFLOPS and energy efficiency of 10.02 GFLOPS/W on a ZYNQ ZC706 FPGA board running at 250 MHz, which outperforms most previous approaches.

关键词： Convolutional neural network field-programmable gate array energy efficiency Roofline model race-to-halt strategy

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FPGA-Based Hardware Design for Scale-Invariant Feature Transform

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IEEE ACCESS 2018年 6卷 43850-43864页

作者： Li, Shih-An Wang, Wei-Yen Pan, Wei-Zheng Hsu, Chen-Chien James Lu, Cheng-Kai Tamkang Univ Dept Elect Engn New Taipei 25137 Taiwan Natl Taiwan Normal Univ Dept Elect Engn Taipei 10610 Taiwan Univ Teknol PETRONAS Dept Elect & Elect Engn Bandar Seri Iskandar 32610 Malaysia

This paper proposes a novel hardware design method of scale-invariant feature transform (SIFT) algorithm for implementation on field-programmable gate array (FPGA). To reduce the computing costs, Gaussian kernels are calculated offline for use in Gaussian filters. To eliminate low-contrast points, the inverse of a Hessian matrix is required for hardware implementation, which results in poor performance because dividers are needed. To solve this problem, this paper presents a new mathematical derivation model to implement the low-contrast detection, avoiding the use of any dividers. For the implementation of the normalization module, a large number of dividers are required by traditional methods, which adversely affects the computational efficiency. This paper presents a new architecture using only one divider to implement the normalization function in hardware. Thanks to the parallel processing architecture proposed to design the image pyramid, SIFT detection, and SIFT descriptor, the computational efficiency of the SIFT algorithm is significantly improved. As a result of the proposed design method, the requirement of logic elements in the FPGA hardware is greatly reduced and system frequency is significantly increased. Experimental results show that the proposed hardware architecture outperforms existing techniques in terms of resource usage and computational efficiency for real-time image processing.

关键词： Scale-invariant feature transform field-programmable gate array parallel processing architecture

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Algorithm for realisation, parameter analysis, and measurement of pipelined separable 3D finite impulse response filters composed of Givens rotation structures

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IET SIGNAL PROCESSING 2018年第7期12卷 857-867页

作者： Poczekajlo, Pawel Wawryn, Krzysztof Koszalin Univ Technol Fac Elect & Comp Sci PL-75453 Koszalin Poland

A novel algorithm for the realisation of an orthogonal digital system performing three-dimensional filtering for a separable transfer function is presented in this study. The algorithm is based on a state-space approach and consists of synthesis and implementation algorithms. A structure composed of Givens rotators and delay elements is obtained. A coordinate rotation digital computer algorithm has been used to implement Givens rotators in a pipelined structure. The obtained structure has been realised on a field-programmable gate array (FPGA) chip and its performance has been evaluated. It achieved good finite precision, good sensitivity of filter amplitude to filter coefficients, less noise, better impulse response, and less FPGA chip occupation. To verify the obtained results, they have been compared to the results obtained using a direct-form structure consisting of adders, multipliers, and delay elements.

关键词： FIR filters transfer functions field programmable gate arrays pipeline processing parameter analysis pipelined separable 3D finite impulse response filter Givens rotation structure orthogonal digital system three-dimensional filtering separable transfer function state-space approach coordinate rotation digital computer algorithm field-programmable gate array FPGA chip occupation

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Efficient Use of On-Chip Memories and Scheduling Techniques to Eliminate the Reconfiguration Overheads in Reconfigurable Systems

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JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS 2019年第14期28卷

作者： Hariharan, I Kannan, M. Anna Univ Dept Elect Engn MIT Campus Chennai 600044 Tamil Nadu India

Modern embedded systems are packed with dedicated field programmable gate arrays (FPGAs) to accelerate the overall system performance. However, the FPGAs are susceptible to reconfiguration overheads. The reconfiguration overheads are mainly because of the configuration data being fetched from the off-chip memory at run-time and also due to the improper management of tasks during execution. To reduce these overheads, our proposed methodology mainly focuses on the prefetch heuristic, reuse technique, and the available memory hierarchy to provide an efficient mapping of tasks over the available memories. Our paper includes a new replacement policy which reduces the overall time and energy reconfiguration overheads for static systems in their subsequent iterations. It is evident from the result that most of the reconfiguration overheads are eliminated when the applications are managed and executed based on our methodology.

关键词： Configuration mapping field-programmable gate array multimedia application optimal-replacement policy reconfiguration overheads scheduling

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EMPLOYING FPGA DSP BLOCKS FOR TIME-TO-DIGITAL CONVERSION

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METROLOGY AND MEASUREMENT SYSTEMS 2019年第4期26卷 631-643页

作者： Kwiatkowski, Pawel Mil Univ Technol Fac Elect Gen S Kaliskiego 2 PL-00918 Warsaw Poland

The paper presents a novel implementation of a time-to-digital converter (TDC) in field-programmable gate array (FPGA) devices. The design employs FPGA digital signal processing (DSP) blocks and gives more than two-fold improvement in mean resolution in comparison with the common conversion method (carry chain-based time coding line). Two TDCs are presented and tested depending on DSP configuration. The converters were implemented in a Kintex-7 FPGA device manufactured by Xilinx in 28 nm CMOS process. The tests performed show possibilities to obtain mean resolution of 4.2 ps but measurement precision is limited to at most 15 ps mainly due to high conversion nonlinearities. The presented solution saves FPGA programmable logic blocks and has an advantage of a wider operation range when compared with a carry chain-based time coding line.

关键词： time-to-digital converter time coding line time interval counter digital signal processing field-programmable gate array

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Fast Neural Network Training on FPGA Using Quasi-Newton Optimization Method

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2018年第8期26卷 1575-1579页

作者： Liu, Qiang Liu, Jia Sang, Ruoyu Li, Jiajun Zhang, Tao Zhang, Qijun Tianjin Univ Sch Microelect Tianjin 300072 Peoples R China Tianjin Univ Sch Elect & Informat Engn Tianjin 300072 Peoples R China

In this brief, a customized and pipelined hardware implementation of the quasi-Newton (QN) method on field-programmable gate array (FPGA) is proposed for fast artificial neural networks onsite training, targeting at the embedded applications. The architecture is scalable to cope with different neural network sizes while it supports batch-mode training. Experimental results demonstrate the superior performance and power efficiency of the proposed implementation over CPU, graphics processing unit, and FPGA QN implementations.

关键词： Custom computing field-programmable gate array neural network training quasi-Newton (QN) method

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Ultra-low-light-level digital still camera for autonomous underwater vehicle

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OPTICAL ENGINEERING 2019年第1期58卷 013106-013106页

作者： Wu, Houde Hou, Yuchen Xu, Wenhai Zhao, Ming Dalian Maritime Univ Informat Sci & Technol Coll Dalian Peoples R China

In deep ocean applications, a camera's viewing range is related to its low-light-level performance. Hence, a high-resolution ultra-low-light-level digital still camera (thereafter L3DSC), designed from the ground up for deep ocean autonomous underwater vehicle (AUV) imaging, is presented. A high-resolution (1024 x 1024) electron-multiplying CCD (EMCCD) is adopted as an image sensor to ensure low-light capability. A thermo electric cooler (TEC) is employed to lower image sensor temperature to promote low-light-level performance. Totem pole circuits that are able to generate 50-V pulse wave at 10 MHz are implemented to drive the EM pin, and power consumption of the circuit is optimized. An EMCCD digital image is buffered in a field-programmable gate array (FPGA) and then transferred through USB interface to a solid-state drive (SSD), which is installed in the image storage unit. The camera is controlled by AUV via Ethernet, and image data stored in the camera could be downloaded via the same interface after AUV retrieved from the sea. The camera module is mounted into a 6000-m depth-rate titanium alloy housing. The diagonal field of view is measured to be 58.4 deg in air. Experiments show that the minimum scene illumination of L3DSC is better than 5 x 10(-4) Lux;underwater imaging distance is longer than 10 m, and total image data capacity is 200 gigabytes. These results demonstrate the camera's low-light-level imaging performance and feasibility for AUV applications. (C) 2019 Society of Photo-Optical Instrumentation Engineers (SPIE)

关键词： low-light-level camera electron-multiplying CCD autonomous underwater vehicle field-programmable gate array

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A Novel FPGA-Based Architecture for Fast Automatic Target Detection in Hyperspectral Images

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REMOTE SENSING 2019年第2期11卷 146-146页

作者： Lei, Jie Wu, Lingyun Li, Yunsong Xie, Weiying Chang, Chein-I Zhang, Jintao Huang, Biying Xidian Univ Sch Telecommun Engn State Key Lab Integrated Serv Networks Xian 710071 Peoples R China Univ Maryland Baltimore Cty Dept Comp Sci & Elect Engn 1000 Hilltop Circle Baltimore MD 21250 USA

Onboard target detection of hyperspectral imagery (HSI), considered as a significant remote sensing application, has gained increasing attention in the latest years. It usually requires processing huge volumes of HSI data in real-time under constraints of low computational complexity and high detection accuracy. Automatic target generation process based on an orthogonal subspace projector (ATGP-OSP) is a well-known automatic target detection algorithm, which is widely used owing to its competitive performance. However, ATGP-OSP has an issue to be deployed onboard in real-time target detection due to its iteratively calculating the inversion of growing matrices and increasing matrix multiplications. To resolve this dilemma, we propose a novel fast implementation of ATGP (Fast-ATGP) while maintaining target detection accuracy of ATGP-OSP. Fast-ATGP takes advantage of simple regular matrix add/multiply operations instead of increasingly complicated matrix inversions to update growing orthogonal projection operator matrices. Furthermore, the updated orthogonal projection operator matrix is replaced by a normalized vector to perform the inner-product operations with each pixel for finding a target per iteration. With these two major optimizations, the computational complexity of ATGP-OSP is substantially reduced. What is more, an FPGA-based implementation of the proposed Fast-ATGP using high-level synthesis (HLS) is developed. Specifically, an efficient architecture containing a bunch of pipelines being executed in parallel is further designed and evaluated on a Xilinx XC7VX690T FPGA. The experimental results demonstrate that our proposed FPGA-based Fast-ATGP is able to automatically detect multiple targets on a commonly used dataset (AVIRIS Cuprite Data) at a high-speed rate of 200 MHz with a significant speedup of nearly 34.3 times that of ATGP-OSP, while retaining nearly the same high detection accuracy.

关键词： hyperspectral image fast automatic target generation process field-programmable gate array high-level synthesis

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