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Pulse discrimination with a Gaussian mixture model on an FPGA

NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH SECTION A-ACCELERATORS SPECTROMETERS DETECTORS AND ASSOCIATED EQUIPMENT 2018年 900卷 1-7页

作者： Simms, Lance M. Blair, Brenton Ruz, Jaime Wurtz, Ron Kaplan, Alan D. Glenn, Andrew Lawrence Livermore Natl Lab Computat Engn Div Livermore CA 94550 USA Lawrence Livermore Natl Lab Div Phys Livermore CA USA

A Gaussian Mixture Model (GMM) based machine learning algorithm has been applied to the problem of gamma/neutron pulse shape discrimination (PSD). The algorithm has been successfully implemented on a standard PC as well as a field programmable gate array (FPGA). Here we describe the GMM classifier and its implementation on these two different types of hardware. We compare the performance of the algorithm on these two platforms against each other, along with other standard techniques applied in PSD. Our results show that the FPGA-based GMM classifier outperforms the standard PSD techniques in terms of classification accuracy at low particle energy and executes more quickly than its CPU-based counterpart.

关键词： Pulse shape discrimination Gaussian mixture model Neutron detection field-programmable gate array

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A reliable and energy-efficient classifier combination scheme for intrusion detection in embedded systems

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COMPUTERS & SECURITY 2018年 78卷 16-32页

作者： Viegas, Eduardo Santin, Altair Oliveira, Luiz Franca, Andre Jasinski, Ricardo Pedroni, Volnei Pontificia Univ Catolica Parana BR-80215901 Curitiba Parana Brazil Univ Fed Parana BR-80060000 Curitiba Parana Brazil Fed Technol Univ Parana BR-80230901 Curitiba Parana Brazil

Embedded systems (electronic systems with a dedicated purpose that are part of larger devices) are increasing their relevance with the rise of the Internet of Things (IoT). Such systems are often resource constrained, battery powered, connected to the intemet, and exposed to an increasing number of threats. An approach to detect such threats is through an anomaly-based intrusion detection with machine-learning techniques. However, most of these techniques were not created with energy efficiency in mind. This paper presents an anomaly-based method for network intrusion detection in embedded systems. The proposed method maintains the classifier reliability even when network traffic contents changes. The reliability is achieved through a new rejection mechanism and a combination of classifiers. The proposed approach is energy-efficient and well suited for hardware implementation. The experiments presented in this paper show that the hardware versions of the machine learning algorithms consume 46% of the energy used by their software counterparts, and the feature extraction and packet capture modules consume 58% and 37% of their respective software counterparts. (C) 2018 Elsevier Ltd. All rights reserved.

关键词： Classifier design and evaluation Feature evaluation and selection Machine learning Energy-aware systems Network-level security and protection System-on-a-chip field-programmable gate array

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Spaceborne synthetic aperture radar imaging mapping methodology based on FPGA-DSP hybrid heterogeneous architecture

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JOURNAL OF ENGINEERING-JOE 2019年第21期2019卷 7313-7317页

作者： Yu, Wenyue Xie, Yizhuang Li, Bingyi Chen, He Liu, Xiaoning Beijing Inst Technol Beijing Key Lab Embedded Real Time Informat Proc Beijing 100081 Peoples R China DFH Satellite Co Ltd Beijing 100081 Peoples R China

With the development of synthetic aperture radar (SAR) technologies in recent years, the huge amount of remote sensing data bring challenges for high-speed transmission and real-time processing. The general platform with GPU, CPU or digital signal processor (DSP) cannot meet the requirement for short delay and low power. Therefore, a field-programmable gate array-digital signal processor (FPGA-DSP) SAR imaging accelerate platform has become a solution for processing performance with a lower latency and power. In this study, an effective mapping strategy is adopted to the FPGA-DSP hybrid heterogeneous architecture to accelerate the processing performance according to the analysis of Chirp Scaling SAR imaging algorithms. As a proof of concept, a FPGA-DSP hybrid heterogeneous accelerating platform is designed and realised. The platform requires 12 s to focus a stripmap SAR raw data with a granularity of 16,384 x 16,384.

关键词： field programmable gate arrays digital signal processing chips synthetic aperture radar spaceborne radar radar imaging spaceborne synthetic aperture radar FPGA-DSP hybrid heterogeneous architecture synthetic aperture radar technologies remote sensing data high-speed transmission real-time processing FPGA-DSP hybrid heterogeneous accelerating platform stripmap SAR raw data field-programmable gate array mapping strategy digital signal processor chirp scaling SAR imaging radar mapping methodology time 12 0 s

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Narrowband hybrid PLC/wireless: Transceiver prototype, hardware resource usage and energy consumption

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AD HOC NETWORKS 2019年 94卷 101945-000页

作者： da Costa, Vinicius Lagrota Rodrigues Fernandes, Victor Ribeiro, Moises Vidal Fed Univ Juiz de Fora UFJF LCom Commun Lab Elect Engn Dept Juiz De Fora Brazil Smarti9 LTD Juiz De Fora MG Brazil

This work discusses a prototype of the so-called narrowband (NB) hybrid power line communication (PLC)/Wireless transceiver, which jointly uses parallel power line and wireless channels for providing data communication to the Industry 4.0, Smart Grids and the Internet of Things applications. The prototype introduces a modified version of the IEEE 1901.2 Standard, which was designed to fulfill NB - PLC applications, to implement the media access control (MAC) sublayer and the physical (PHY) layer of a hybrid transceiver that is capable of transmitting data through both power line and wireless channels. Therefore, the NB hybrid PLC/Wireless transceiver prototype is compatible with a NB - PLC transceiver that makes use of the IEEE 1901.2 Standard. Moreover, both transceivers can constitute heterogeneous data communication networks that are capable of improving reliability and coverage. Furthermore, based on a field-programmable gate array (FPGA) device, we discuss the hardware resource usage and energy consumption analyses and the hardware feasibility of implementing a bit correction technique at the link layer of the NB hybrid PLC/Wireless transceiver prototype. We show that the signal/data processing block of the proposed transceiver demands only 1.12 times the energy consumption required by a NB - PLC transceiver based on the IEEE 1901.2 Standard. Moreover, the designed roadmap for this kind of hybrid PLC/wireless transceiver demands 1.5 times the hardware resource usage in comparison to the implementation of the PLC transceiver based on the IEEE 1901.2 Standard. Finally, we show that up 5 bits can be corrected at the link layer level without increasing the clock frequency. (C) 2019 Elsevier B.V. All rights reserved.

关键词： Power line communication Wireless communication field-programmable gate array Internet of Things Smart grid communication Hybrid data communication

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Gaussian random number generator: Implemented in FPGA for quantum key distribution

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INTERNATIONAL JOURNAL OF NUMERICAL MODELLING-ELECTRONIC NETWORKS DEVICES AND fieldS 2019年第3期32卷 e2554-e2554页

作者： Hu, Yue Wu, Yan Chen, Yi Wan, Guo Chun Tong, Mei Song Tongji Univ Coll Elect & Informat Engn Shanghai 201804 Peoples R China

Quantum key distribution is the process of using quantum communication to establish a shared key between two parties. It has been demonstrated the unconditional security and effective communication of quantum communication system can be guaranteed by an excellent Gaussian random number (GRN) generator with high speed and an extended random period. In this paper, we propose to construct the Gaussian random number generator by using field-programmable gate array (FPGA), which is able to process large data in high speed. We also compare three algorithms of GRN generation: Box-Muller algorithm, polarization decision algorithm, and central limit algorithm. We demonstrate that the polarization decision algorithm implemented in FPGA requires less computing resources and also produces a high-quality GRN through the null hypothesis test.

关键词： Gaussian random numbers quantum key distribution field-programmable gate array numerical modeling

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An abstraction layer enabling pervasive hardware-reconfigurable systems

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INTERNATIONAL JOURNAL OF EMBEDDED SYSTEMS 2018年第5期10卷 366-377页

作者： Cilardo, Alessandro Mazzocca, Nicola Prinetto, Paolo Univ Naples Federico II Via Claudio 21 I-80125 Naples Italy Politecn Torino Corso Duca Abruzzi 24 I-10129 Turin Italy

field-programmable gate array technologies are creating a new range of challenges for pervasive and ubiquitous systems. Revisiting and extending approaches borrowed from the purely software domain is a fundamental opportunity in this scenario. In particular, this paper addresses code mobility, a well-established approach used to dynamically adapt a distributed system based on the actual application needs, and extends it to a deep code mobility concept, allowing 'logical' hardware components to be migrated across a pervasive infrastructure. The work presents the architecture and the prototype implementation of a reconfigurable computing framework providing full support to deep code mobility through an abstraction layer which exposes a portable view of the underlying reconfigurable hardware. The paper then thoroughly discusses two application scenarios, hardware-accelerated distributed data mining and autonomous online testing, confirming the impact of deep code mobility in real-world pervasive computing contexts.

关键词： pervasive computing ubiquitous systems code mobility reconfigurable computing field-programmable gate array FPGA adaptive systems

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Parallelism Optimized Architecture on FPGA for Real-Time Traffic Light Detection

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IEEE ACCESS 2019年 7卷 178167-178176页

作者： Wu, Xue-Hua Hu, Renjie Bao, Yu-Qing Southeast Univ Sch Elect Engn Nanjing 210096 Peoples R China Nanjing Normal Univ Sch Elect & Automat Engn Nanjing 210023 Peoples R China

In this paper, a portable assistance system is designed to help the visually impaired to detect the traffic light. The designed system is realized on the basis of the AdaBoost algorithm, which is fast and robust in object detections. In order to accelerate the AdaBoost-based approach, a flexible parallel architecture is implemented on the field-programmable gate array (FPGA) platform. The architecture is designed utilizing the parallelism of computations in the AdaBoost-based detection. The computations of the window integral image are implemented in parallel, and the confidences of the weak classifiers are calculated in parallel. The parameters of the weak classifiers are trained by the AdaBoost algorithm with multi-layer features in the MATLAB software, and then are configured on the FPGA platform via the Vivado design suite before the detection process. The parallelism optimized architecture is implemented on an Artix-7 FPGA at 200 MHZ. Experiments show that it can detect the traffic light in videos with a rate of 30 frames per second (fps).

关键词： AdaBoost algorithm field-programmable gate array integral image parallel architecture traffic light detection

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An FPGA-Based Ultra-High-Speed Object Detection Algorithm with Multi-Frame Information Fusion

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SENSORS 2019年第17期19卷 3707-3707页

作者： Long, Xianlei Hu, Shenhua Hu, Yiming Gu, Qingyi Ishii, Idaku Chinese Acad Sci Inst Automat Res Ctr Precis Sensing & Control Beijing 100190 Peoples R China Univ Chinese Acad Sci Sch Artificial Intelligence Beijing 101408 Peoples R China Hiroshima Univ Dept Syst Cybernet Robot Lab Hiroshima 7398527 Japan

An ultra-high-speed algorithm based on Histogram of Oriented Gradient (HOG) and Support Vector Machine (SVM) for hardware implementation at 10,000 frames per second (FPS) under complex backgrounds is proposed for object detection. The algorithm is implemented on the field-programmable gate array (FPGA) in the high-speed-vision platform, in which 64 pixels are input per clock cycle. The high pixel parallelism of the vision platform limits its performance, as it is difficult to reduce the strides between detection windows below 16 pixels, thus introduce non-negligible deviation of object detection. In addition, limited by the transmission bandwidth, only one frame in every four frames can be transmitted to PC for post-processing, that is, 75% image information is wasted. To overcome the mentioned problem, a multi-frame information fusion model is proposed in this paper. Image data and synchronization signals are first regenerated according to image frame numbers. The maximum HOG feature value and corresponding coordinates of each frame are stored in the bottom of the image with that of adjacent frames'. The compensated ones will be obtained through information fusion with the confidence of continuous frames. Several experiments are conducted to demonstrate the performance of the proposed algorithm. As the evaluation result shows, the deviation is reduced with our proposed method compared with the existing one.

关键词： ultra-high-speed vision object detection field-programmable gate array histogram of oriented gradient multi-frame information fusion model

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Research on near-field focusing algorithm of reconfigurable reflect-array

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JOURNAL OF ENGINEERING-JOE 2019年第19期2019卷 5801-5804页

作者： Liu, HongYan Zheng, Pei Wang, Chao Guo, Lei Zhang, XinYu Natl Key Lab Sci & Technol Test Phys & Numer Math Beijing Peoples R China

In this study, the near-field beam focusing algorithm of reconfigurable reflect array for security imaging application is proposed. The proposed near-field focusing algorithm is based on classic array method, which is usually adopted for far-field pattern calculation. In order to satisfy the near-field imaging application, the imaging distance is added to array method, and the improved formula can calculate the shifting phase of every array element precisely. In addition, due to discrete phase characteristic of reconfigurable reflect array, a phase choice method based on trigonometric function is used in authors' design. Based on the proposed algorithm, the shifting phase of every element is calculated and obtained the simulated beam focusing patterns. Meanwhile, the calculated shifting phase is written to whole array by field-programmable gate array, the near-field beam scanning patterns is measured and the measured results are in good agreement with the simulated ones.

关键词： field programmable gate arrays reflectarray antennas microwave imaging microwave antenna arrays security focusing antenna radiation patterns scanning antennas near-field imaging application imaging distance field-programmable gate array near-field focusing algorithm reconfigurable reflectarray near-field beam focusing algorithm security imaging

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Space Vector Modulation Implementation on RTOS/FPGA Embedded System 3

Space Vector Modulation Implementation on RTOS/FPGA Embedded...

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3rd IEEE International Conference on Smart Systems and Technologies (SST)

作者： Ugljar, Marjan Bensic, Tin Barukcic, Marinko Fac Elect Engn Comp Sci & Informat Technol Osijek Osijek Croatia

ISBN: (纸本)9781538671894

The paper proposes a method for implementing Space Vector Modulation (SVM) on the CompactRio embedded platform. The concept of space vectors is presented and the mathematical model of the SVM is derived. A description of the CompactRio RTOS/FPGA Embedded platform is presented. A new method for analyzing and generating SVM gate control pulses is proposed. The proposed method to generate SVM pulses based on the symmetric SVM switching pattern using the clock of the FPGA processor is implemented and performance studied.

关键词： Voltage Source Inverter Space Vector Modulation Real-Time Operating System field-programmable gate array NI CompactRio

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