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A review of demodulation techniques for amplitude-modulation atomic force microscopy

BEILSTEIN JOURNAL OF NANOTECHNOLOGY 2017年第1期8卷 1407-1426页

作者： Ruppert, Michael G. Harcombe, David M. Ragazzon, Michael R. P. Moheimani, S. O. Reza Fleming, Andrew J. Univ Newcastle Sch Elect Engn & Comp Callaghan NSW 2308 Australia Norwegian Univ Sci & Technol NTNU Dept Engn Cybernet Trondheim Norway Univ Texas Dallas Dept Mech Engn Richardson TX 75083 USA

In this review paper, traditional and novel demodulation methods applicable to amplitude-modulation atomic force microscopy are implemented on a widely used digital processing system. As a crucial bandwidth-limiting component in the z-axis feedback loop of an atomic force microscope, the purpose of the demodulator is to obtain estimates of amplitude and phase of the cantilever deflection signal in the presence of sensor noise or additional distinct frequency components. Specifically for modern multifrequency techniques, where higher harmonic and/or higher eigenmode contributions are present in the oscillation signal, the fidelity of the estimates obtained from some demodulation techniques is not guaranteed. To enable a rigorous comparison, the performance metrics tracking bandwidth, implementation complexity and sensitivity to other frequency components are experimentally evaluated for each method. Finally, the significance of an adequate demodulator bandwidth is highlighted during high-speed tapping-mode atomic force microscopy experiments in constant-height mode.

关键词： amplitude estimation atomic force microscopy amplitude modulation digital signal processing field-programmable gate array

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Set/Reset Switching Model of Cu Atom Switch Based on Electrolysis

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IEEE TRANSACTIONS ON ELECTRON DEVICES 2017年第4期64卷 1812-1817页

作者： Tada, Munehiro Sakamoto, Toshitsugu NEC Corp Ltd Tsukuba Ibaraki 3058501 Japan

A set/reset switching model of Cu atom switch based on electrolysis is newly proposed. A nanometer-thick solid electrolyte gives a high electric field of similar to 3.3 MV/cm in the solid electrolyte at 2 V, enabling an ionization of Cu and a formation of Cu bridge. It is revealed that the switching voltage depends on the resistance of electrolyte, where the modified Faraday's law of electrolysis with exponential factors on current and time well falls on the experimental on-resistance. The proposed simple compact model is useful for estimating the resistance of the Cu atom switch programmed by any conditions.

关键词： Atom switch conductive-bridging Random access memory field-programmable gate array nonvolatile memory programmable logic device polymer reconfigurable logic solid electrolyte

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Concurrent Dual-Band Digital Predistortion Using 2-D Lookup Tables With Bilinear Interpolation and Extrapolation: Direct Least Squares Coefficient Adaptation

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IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES 2017年第4期65卷 1381-1393页

作者： Molina, Albert Rajamani, Kannan Azadet, Kamran Intel Corp Madrid 28020 Spain Intel Corp Allentown PA 18019 USA Intel Corp Santa Clara CA USA

In this paper, we present a method to implement concurrent dual-band digital predistortion (DPD) models using 2-D lookup tables (LUTs) with bilinear interpolation and extrapolation. We introduce the required set of basis functions to describe this model. The DPD output is expressed as a linear combination of these basis functions and we show how to directly estimate the coefficients using least squares. We introduce a flexible 2-D bilinear extrapolation scheme that is ideally suited to dual-band signals with high peak-to-average power ratio. We show how these are needed when digital predistortion is implemented in conjunction with automatic gain control. We also introduce example dual-band polynomial models with memory and show how to create a similar memory model based on 2-D lookup tables with bilinear interpolation. One such model is the dual-band generalized memory polynomial model. Laboratory experiments are performed using such a 2-D LUT with bilinear interpolation model.

关键词： Automatic gain control (AGC) bilinear extrapolation bilinear interpolation cellular base station digital predistortion (DPD) DPD adaptation dual band field-programmable gate array generalized memory polynomial (GMP) nonlinear distortion power amplifiers (PAs) 2-D lookup table (LUT) vector processor

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Offloading Collective Operations to programmable Logic

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IEEE MICRO 2017年第5期37卷 52-60页

作者： Arap, Omer Brasilino, Lucas R. B. Kissel, Ezra Shroyer, Alexander Swany, Martin Indiana Univ Bloomington IN 47405 USA Indiana Univ Intelligent Syst Engn Dept Bloomington IN 47405 USA Indiana Univ Experience Microcontroller Data Acquisit Devices Bloomington IN 47405 USA Indiana Univ Intelligent Syst Engn Dept Sch Informat & Comp Bloomington IN 47405 USA

In this article, the authors present a framework for offloading collective operations to programmable logic for use in applications using the Message Passing Interface (MPI). They evaluate their approach on the Xilinx Zynq system on a chip and the NetFPGA, a network interface card based on a field-programmable gate array. Results are presented from microbenchmarks and a benchmark scientific application.

关键词： Algorithm design and analysis collective operations field programmable gate arrays field-programmable gate array FPGA message passing interface MPI Network interfaces Ports (Computers) Programming Random access memory SoC system on a chip Zynq

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DRAF: A LOW-POWER DRAM-BASED RECONFIGURABLE ACCELERATION FABRIC

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IEEE MICRO 2017年第3期37卷 70-78页

作者： Gao, Mingyu Delimitrou, Christina Niu, Dimin Malladi, Krishna T. Zheng, Hongzhong Brennan, Bob Kozyrakis, Christos Stanford Univ Dept Elect Engn Stanford CA 94305 USA Cornell Univ Dept Elect & Comp Engn Ithaca NY 14853 USA Cornell Univ Dept Comp Sci Ithaca NY 14853 USA Samsung Semicond US R&D Ctr Memory Solut Lab San Jose CA USA Stanford Univ Dept Comp Sci Stanford CA 94305 USA

The DRAM-Based Reconfigurable Acceleration Fabric (DRAF) uses commodity DRAM technology to implement a bit-level, reconfigurable fabric that improves area density by 10 times and power consumption by more than 3 times over conventional field-programmable gate arrays. Latency overlapping and multicontext support allow DRAF to meet the performance and density requirements of demanding applications in datacenter and mobile environments.

关键词： DRAM field-programmable gate array FPGA low power reconfigurable logic

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An Implementation of Automatic and Network-Controlled Tea Bag Brewing Machine

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资讯科技国际期刊 2018年第2期12卷 45-49页

作者： Wen-Chung Tsai Ming-Hong Lu Shi-Xiang Zhu Yu-Ping Huang Ching-Yi Chen Che-Jung Kuo

In this paper, we propose an automatic tea bag brewing machine that can be remotely controlled via Internet. Functions of control were implemented by an hardware-software co-design fashion and programmed into a FPGA (field-programmable gate array) embedded system development board. Additionally, the development board was connected with several components including a 6-degree and three-dimensional rotating mechanical arm, a thermos bottle, and a water injection control circuit. As such, the proposed IoT-type tea bag brewing machine can be realized. In operation, according to different requirements, user can choose an alternative tea bag and assign different water volumes. By using a networked device such as smart-phone to send control messages to the implemented machine remotely, the mechanical arm of the machine can automatically execute the process of brewing up a cup of tea to minimize the labors' interventions periodically.

关键词： field-programmable gate array Servo Motor Mechanical Arm Internet of Things Smart-Phone Tea Bag Brewing

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An FPGA-Based Unscented Kalman Filter for System-On-Chip Applications

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2017年第4期64卷 447-451页

作者： Soh, Jeremy Wu, Xiaofeng Univ Sydney Aerosp Mech & Mechatron Engn Sydney NSW 2006 Australia

The demand for fast and accurate state estimation in embedded systems has been increasing lately, due at least in part to mobile robotics such as an unmanned aerial vehicle (UAV). The desire to maintain high performance but with compact form factors leads to implementation issues, particularly with more complex systems. A hardware-based approach using field-programmable gate arrays may be able to alleviate these issues but tends to have a more complicated development process than traditional software-based approaches. In order to simplify development and promote portability between embedded applications, a hardware/software codesign of the unscented Kalman filter is presented. An example implementation (N = 18) of the hardware IP core only is presented using the Zynq-7000 XC7Z045 with synthesis, power, and timing results for the 1, 2, 5, and 10 processing-element cases.

关键词： Coprocessors field-programmable gate array Kalman filters nonlinear filters signal processing system-on-chip

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DATuner: An Extensible Distributed Autotuning Framework for FPGA Design and Design Automation: (Abstract Only) 18

DATuner: An Extensible Distributed Autotuning Framework for ...

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Proceedings of the 2018 ACM/SIGDA International Symposium on field-programmable gate arrays

作者： Gai Liu Ecenur Ustun Shaojie Xiang Chang Xu Guojie Luo Zhiru Zhang Cornell University Ithaca NY USA IBM Research China Beijing China Peking University Beijing China

ISBN: (纸本)9781450356145

Mainstream FPGA tools contain an extensive set of user-controlled compilation options and internal optimization strategies that significantly impact the design quality. These compilation and optimization parameters create a complex design space that human designers may not be able to effectively explore in a time-efficient manner. In this work we describe DATuner, an open-source extensible distributed autotuning framework for optimizing FPGA designs and design automation tools using an ensemble of search techniques managed by multi-armed bandit algorithms. DATuner is designed for a distributed environment that uses parallel searches to amortize the significant runtime overhead of the CAD tools. DATuner provides convenient interface for extension to user-supplied tools, which enables the end users to apply DATuner to design tools/flows of their interest. We demonstrate the effectiveness and extensibility of DATuner using three case studies, which include clock frequency optimization for FPGA compilation, fixed-point optimization, and autotuning logic synthesis transformations.

关键词： field-programmable gate array design automation distributed autotuning

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Design of Vehicle License Plate Positioning System Based on FPGA

Design of Vehicle License Plate Positioning System Based on ...

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第37届中国控制会议

作者： Yandong Jia Chunyang Wang Jilin Province Advanced Control Technology and Intelligent Automation Equipment Research Engineering Lab Changchun University of Science and Technology

Traditional License Plate Positioning(LPP) systems always utilize complex structures, resulting in low processing speed. In this paper, we propose an identification system for vehicle license plates based on field-programmable gate array(FPGA). The improved Sobel edge detection algorithm is applied to conduct image preprocessing, and the watershed algorithm is used to identify the plates. This leads to a simplified system structure and a higher speed for the plates identification. This system uses a camera to collect image information, the FPGA to conduct image reception and processing, and a monitor to display the identification results. After debugging and executing, the design is proved to be of high performance, and is capable of applying to practical engineering projects.

关键词： License Plate Positioning field-programmable gate array image preprocessing

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Real-Time Demonstration of Low-Complexity Time-Domain Chromatic Dispersion Equalization 19

Real-Time Demonstration of Low-Complexity Time-Domain Chroma...

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19th International Conference on Transparent Optical Networks (ICTON)

作者： Martins, Celestino S. Amado, Sofia B. Ferreira, Ricardo M. Shahpari, Ali Teixeira, Antonio L. Guiomar, Fernando P. Pinto, Armando N. Univ Aveiro Dept Elect Telecommun & Informat Campus Univ Santiago P-3810193 Aveiro Portugal Inst Telecomunicacoes Campus Univ Santiago P-3810193 Aveiro Portugal Politecn Torino Dipartimento Elettron & Telecomunicaz Corso Duca Abruzzi 24 I-10129 Turin Italy

ISBN: (纸本)9781538608593

We demonstrate real-time CD equalization (CDE) for coherent optical transmission systems using a low complexity time-domain (TD) multiplierless finite-impulse response (FIR)-based equalizer, based on a field-programmable gate array (FPGA) implementation. The real-time operation is performed for a single-channel 2.5 Gb/s QPSK optical signal with a performance penalty of only similar to 0.15 dB with respect to the maximum performance. The hardware complexity is also evaluated in terms of occupation in a Virtex-6 FPGA-XC6VLX240T, revealing the high efficiency of the proposed CDE algorithm.

关键词： optical communications coherent detection digital signal processing real-time hardware implementation field-programmable gate array

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