检索结果-内蒙古大学图书馆

IEEE International Conference on Systems, Man, and Cybernetics (SMC)

作者： Sung, Guo-Ming Chou, Wen-Duen Chiu, Tzu-Hsuan Natl Taipei Univ Technol Dept Elect Engn Taipei Taiwan

ISBN: (纸本)9781509018970

This paper presents an optical transceiver, whose packet process is completed with deficit round robin (DRR) and RS232 interface, for optical synchronous optical networking (SONET) which can service on both asymmetric digital subscriber line (ADSL) and optical packet switching (OPS). To resolve the clock jitter, not only the cycle decision but also the reset function are used to synchronize the clock waveform. In the proposed DRR, it performs the packet process with low delay and low loss. Moreover, the RS232 interface, which is integrated with the field-programmable gate array (FPGA) board, is adopted due to its easy implementation. The processing data will be queued with DRR and be sent to electrical/optical (E/O) converter from the RS232 port on FPGA board (Transmitter). Passing through the optical fiber, the packet from transmitter is sent to the O/E converter and then received at the RS232 port on another FPGA board. The received electrical packet will be displayed on the seven-segment display of FPGA board to verify the transceiver function for SONET. Note that the proposed architecture is designed with Verilog hardware describe language (Verilog HDL). According to the measured results, the data transfer rate is 115,200 bps with the FPGA operating frequency of 50 MHz and the fiber distance of 5 km.

关键词： defict round robin RS232 interface transceiver synchronous optical netwoking asymmetric digital subscriber line hardware describe language field-programmable gate array

来源：评论

学校读者我要写书评

暂无评论

An Evaluation of Vivado HLS for Efficient System Design 58

An Evaluation of Vivado HLS for Efficient System Design

引用

58th ELMAR International Symposium

作者： Georgopoulos, Konstantinos Chrysos, Grigorios Malakonakis, Pavlos Nikitakis, Antonis Tampouratzis, Nikos Dollas, Apostolos Pnevmatikatos, Dionisios Papaefstathiou, Yannis Tech Univ Crete Microprocessor & Hardware Lab Khania Greece

ISBN: (纸本)9789531842211

High-Level Synthesis (HLS) tools are hailed as one of the most promising ways to bridge the design productivity gap, especially for reconfigurable systems. These tools increase designer productivity at a possible performance and/or silicon cost, although the designer can play a significant role in the minimisation of both. Currently, one of the key challenges for the designer is to efficiently use the vendor-defined methodology and the design guidelines of the HLS tool. Hence, this work aims at assisting designers in taking full advantage and making optimal use of the official HLS methodology when implementing three fundamental algorithms used in a variety of video and image processing applications. One is a sorting algorithm while the other two are algorithms used in traversing tree/graph data structures. The work presented here concerns a highly popular HLS tool, namely Vivado HLS, and the experiences and analysis of the authors helps in the efficient use of the toolset, which can significantly increase design productivity when compared to the naive datasheet-based approach;the performance of all the resulting synthesisable models is also provided for completeness.

关键词： High-Level Synthesis Reconfigurable Computing field-programmable gate array Data Structures

来源：评论

学校读者我要写书评

暂无评论

Digital Coherent Receiver Technique for Onboard Receiver of Future Optical Data Relay System 28

Digital Coherent Receiver Technique for Onboard Receiver of ...

引用

Conference on Free-Space Laser Communication and Atmospheric Propagation XXVIII

作者： Araki, Tomohiro Japan Aerosp Explorat Agcy JAXA Res & Dev Directorate 2-1-1 Sengen Tsukuba Ibaraki 3058505 Japan

ISBN: (纸本)9781628419740

A digital coherent receiver technique for an onboard receiver for use in a future space optical communication system is investigated. Digital coherent technologies comprising coherent detection and digital signal processing are confirmed to possibly increase the signal speed, improve the receiver sensitivity, and extend tolerance for the Doppler frequency shift. As a facet of expandability, the concept of a multichannel-rate receiver using a digital coherent technique is introduced. Experimental results using 2.5 Gbps DBPSK signal light demodulation are presented together with future issues involved in implementation. This study confirms that the digital coherent receiver has higher expandability than other detection techniques.

关键词： Digital Coherent Space Optical Communication Doppler Frequency Shift field-programmable gate array

来源：评论

学校读者我要写书评

暂无评论

An-FPGA based classification system by using a neural network and an improved particle swarm optimization algorithm 8

An-FPGA based classification system by using a neural networ...

引用

Joint 8th International Conference on Soft Computing and Intelligent Systems (SCIS) / 17th International Symposium on Advanced Intelligent Systems (ISIS)

作者： Dang, Tuan Linh Hoshino, Yukinobu Kochi Univ Technol Sch Syst Engn Kochi Japan

ISBN: (纸本)9781509026784

This paper presents a development of a soft intelligent system on chip. This system is used to solve the classification problem. In this system, a neural network is trained by the particle swarm optimization (PSO) algorithm. This algorithm is hardware implemented on a real device. An improved version of the standard PSO algorithm called the PSOseed algorithm is also introduced in this paper in order to reduce the possibility when the standard PSO gets stuck in the local minimum. The experimental results show that the neural network trained by the particle swarm optimization algorithm was successful hardware implemented. In addition, the PSOseed algorithm also obtained a better performance than the standard PSO algorithm in our experiments.

关键词： field-programmable gate array neural network particle swarm optimization soft intelligent systems on chip velocity control

来源：评论

学校读者我要写书评

暂无评论

A Robust Approach to the Generation of High Quality Random Numbers 2

A Robust Approach to the Generation of High Quality Random N...

引用

Conference on Quantum Information Science and Technology II

作者： Bisadi, Zahra Fontana, Giorgio Moser, Enrico Pucker, Georg Pavesi, Lorenzo Univ Trento Dept Phys Nanosci Lab Via Sommarive 14 I-38123 Povo Trento Italy Bruno Kessler Fdn Ctr Mat & Microsyst Via Sommarive 18 I-38123 Povo Trento Italy

ISBN: (数字)9781510603974

ISBN: (纸本)9781510603967;9781510603974

A random number generation approach comprising a silicon nanocrystals LED (Si-NCs LED), silicon single photon avalanche photodiode (Si SPAD) and a field-programmable gate array (FPGA) is introduced. The Si-NCs LED is the source of entropy with photon emission in the visible range detectable by silicon detectors allowing the fabrication of an all-silicon-based device. The proposed quantum random number generator (QRNG) is robust against variations of the internal and external parameters such as aging of the components, changing temperature, the ambient interferences and the silicon detector artifacts. The raw data show high quality of randomness and passed all the statistical tests in National Institute of Standards and Technology (NIST) tests suite without the application of a post-processing algorithm. The efficiency of random number generation is 4-bits per detected photon.

关键词： Robust quantum random number generation silicon nanocrystals LED silicon single photon avalanche photodiode field-programmable gate array NIST tests suite

来源：评论

学校读者我要写书评

暂无评论

An Efficient Algorithm Strategy for Synchronous Rectification used in LLC Resonant Converters 42

An Efficient Algorithm Strategy for Synchronous Rectificatio...

引用

42nd Annual Conference of the IEEE-Industrial-Electronics-Society (IECON)

作者： Hong, Liang Ma, Hao Wang, Jun Du, Jianhua Wang, Binlei Zhejiang Univ Coll Elect Engn Hangzhou 310027 Peoples R China Beijing Inst Control Engn Beijing 100190 Peoples R China

ISBN: (纸本)9781509034741

In this paper, an efficient algorithm strategy for synchronous rectification (SR) used in LLC resonant converters is proposed. The output voltage and the primary resonant inductor current of LLC converter are combined together to produce suitable drive signals for SR in the below resonance mode. In the other resonance modes, the drive signals for SR are synchronous with the drive signals of corresponding primary switches. In order to validate the feasibility of the proposed algorithm strategy, a 300W prototype with 100V input voltage, 25V output voltage is implemented using field-programmable gate array (FPGA). The measured maximum efficiency is 92.1% and the overall efficiency is higher than the one with conventional drive method for SR.

关键词： algorithm strategy LLC resonant converters field-programmable gate array synchronous rectification

来源：评论

学校读者我要写书评

暂无评论

Low Cost Resilient Regular Expression Matching on FPGAs 29

Low Cost Resilient Regular Expression Matching on FPGAs

引用

29th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

作者： Leipnitz, Marcos T. de Souza, Eduardo Nunes Nazar, Gabriel L. Univ Fed Rio Grande do Sul Inst Informat Porto Alegre RS Brazil

ISBN: (纸本)9781509036233

The Network Function Virtualization (NFV) paradigm promises to make networks more scalable and flexible by decoupling the network functions (NFs) from dedicated and vendor-specific hardware. However, network and compute intensive NFs may be difficult to virtualize without performance degradation. In this context, field-programmable gate arrays (FPGAs) have been shown to be a good option for hardware acceleration of virtual NFs that require high throughput, without deviating from the concept of an NFV infrastructure which aims at high flexibility. Regular expression matching is an important and compute intensive mechanism used to perform Deep Packet Inspection, which can be FPGA-accelerated to meet performance constraints. This solution, however, introduces new challenges regarding dependability requirements. Particularly for FPGAs, soft errors on the configuration memory are a significant dependability threat. Therefore, in this work we evaluate the effects of configuration faults on the functionality of FPGA-based regular expression matching engines and propose fault tolerance mechanisms to improve its resilience against such faults.

关键词： Network Function Virtualization field-programmable gate array Regular Expression Matching Fault Tolerance

来源：评论

学校读者我要写书评

暂无评论

A computational approach to real-time image processing for serial time-encoded amplified microscopy

A computational approach to real-time image processing for s...

引用

Conference on High-Speed Biomedical Imaging and Spectroscopy - Toward Big Data Instrumentation and Management

作者： Oikawa, Minoru Hiyama, Daisuke Hirayama, Ryuji Hasegawa, Satoki Endo, Yutaka Sugie, Takahisa Tsumura, Norimichi Kuroshima, Mai Maki, Masanori Okada, Genki Lei, Cheng Ozeki, Yasuyuki Goda, Keisuke Shimobaba, Tomoyoshi Chiba Univ Inage Ku Yayoi Cho Chiba 2638522 Japan Univ Tokyo Bunkyo Ku Tokyo 1130033 Japan

ISBN: (纸本)9781628419542

High-speed imaging is an indispensable technique, particularly for identifying or analyzing fast-moving objects. The serial time-encoded amplified microscopy (STEAM) technique was proposed to enable us to capture images with a frame rate 1,000 times faster than using conventional methods such as CCD (charge -coupled device) cameras. The application of this high-speed STEAM imaging technique to a real-time system, such as flow cytometry for a cell-sorting system, requires successively processing a large number of captured images with high throughput in real time. We are now developing a high-speed flow cytometer system including a STEAM camera. In this paper, we describe our approach to processing these large amounts of image data in real time. We use an analog-to-digital converter that has up to 7.0G samples/s and 8 -bit resolution for capturing the output voltage signal that involves grayscale images from the STEAM camera. Therefore the direct data output from the STEAM camera generates 7.0G byte/s continuously. We provided a field -programmable gate array (FPGA) device as a digital signal pre-processor for image reconstruction and finding objects in a microfluidic channel with high data rates in real time. We also utilized graphics processing unit (GPU) devices for accelerating the calculation speed of identification of the reconstructed images. We built our prototype system, which including a STEAM camera, a FPGA device and a GPU device, and evaluated its performance in real-time identification of small particles (beads), as virtual biological cells, flowing through a microfluidic channel.

关键词： imaging real time STEAM field-programmable gate array graphics processing unit CUDA

来源：评论

学校读者我要写书评

暂无评论

DESIGN AND IMPLEMENTATION OF FPGA-BASED MULTI-RATE BPSK-QPSK MODEM WITH FOCUS ON CARRIER RECOVERY AND TIME SYNCHRONIZATION

DESIGN AND IMPLEMENTATION OF FPGA-BASED MULTI-RATE BPSK-QPSK...

引用

作者： SEYED ALI HASSANI Tampere University of Technology

学位级别：硕士

Regarding the high performance and reconfigurability of field programmable gate Ar- rays (FPGAs), many recent software defined radio (SDR) systems are currently being designed and developed on them. On the other hand, a wide variety of applications in communication systems benefits from Phase-Shift Keying (PSK) modulation. There- fore, with respect to practical constraints and limitations, design and implementation of a robust and efficient FPGA-based structure for PSK modulation is an attractive subject of study. In practice, there is an unavoidable oscillator frequency difference between the transmit- ter and receiver which poses many challenges for designers. This frequency offset makes carrier recovery and time synchronization as two essential functions of every receiver. The possible solution lies in the closed loop control techniques. In other words, without feedback-based controllers, acceptable performance in a digital radio link is unachievable. The Costas Loop is one of the most effective methods for carrier recovery and its advantage over other methods is that the error signal in the feedback loop is twice as accurate. The Gardner time synchronization method is also introduced as a closed loop clock and data recovery technique and, regarding to its performance, is a potential candidate to be implemented on FPGA-based platforms. The main body of this thesis work is related to the realization aspects of these methods on FPGA. The thesis spans from the design and implementation of a baseband digital transceiver to connecting it to a radio frequency device, forming a Binary/Quadrature PSK modem. The introduced platform is developed on National Instruments Universal Software Radio Peripheral (NI USRP) equipped with a Xilinx Kintex 7 FPGA. Many case studies were conducted to evaluate the performance of similar systems con- sidering Signal to Noise Ratio (SNR). In this study, in addition to SNR, the effective- ness of the implemented transceiver has been evaluat

关键词： Software Defined Radio Phase Shift Keying Modulation Carrier Recovery Clock and Data Recovery Time Synchronization field-programmable gate array

来源：评论

学校读者我要写书评

暂无评论

Slant transform applied to electric power quality detection with field programmable gate array design enhanced

引用

INTERNATIONAL JOURNAL OF ELECTRICAL POWER & ENERGY SYSTEMS 2010年第5期32卷 428-432页

作者： Hsieh, Cheng-Tao Lin, Jeu-Min Huang, Shyh-Jier Natl Cheng Kung Univ Dept Elect Engn Tainan 70101 Taiwan Kun Shan Univ Dept Elect Engn Tainan Taiwan Far E Univ Dept Elect Engn Tainan Taiwan

In this paper, a slantlet transform is proposed with the field-programmable gate array (FPGA) hardware realization for electrical power system disturbance detection. By embedding the slantlet functions into wavelet basis, the method is anticipated to increase the capability of signal discrimination, hence improving the grasping the disturbance intrusion. Furthermore, with the hardware realization of FPGA chip, the practicality of the method can be better ensured. In order to validate the effectiveness of the proposed approach, several scenarios have been considered and verified with good agreement. (C) 2009 Elsevier Ltd. All rights reserved.

关键词： Electrical power system disturbances Slantlet transform field-programmable gate array

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：