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An FPGA chaos-based PWM technique combined with simple passive filter for effective EMI spectral peak reduction in DC-DC converter

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Advances in Power Electronics 2014年第unknown期2014卷

作者： Natarajan, Sudhakar Natarajan, Rajasekar School of Electrical Engineering VIT University Vellore Tamilnadu 632014 India

A new and simple but effective electromagnetic interference suppression technique based on field programmable logic array (FPGA) technology to provide a significant EMI noise attenuation in DC-DC converters is discussed. The voltage controlled boost converter for EMI reduction is analyzed using FFT under traditional PWM technique and chaotic mode operation. This technique aids the DC-DC converters to comply in specified EMI limits and replace conventional bulky passive filter with a simple passive filter. A prototype model has been tested and hardware results show significant reduction of EMI in chaotic mode operation of the boost converter. © 2014 Sudhakar Natarajan and Rajasekar Natarajan.

关键词： Converter DC-to-DC converter field-programmable gate array

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The Implementation of an Amplitude-Locked Loop for Digital Communication Chip Design

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WIRELESS PERSONAL COMMUNICATIONS 2013年第4期72卷 2773-2801页

作者： Jong, Gwo-Jia Chen, Yin-Chih Huang, Chen-Shen Yu, Gwo-Jeng Horng, Gwo-Jiun Natl Kaohsiung Univ Appl Sci Inst Elect Engn Kaohsiung 807 Taiwan Cheng Shiu Univ Dept Comp Sci & Informat Engn Kaohsiung Taiwan Natl Cheng Kung Univ Dept Comp Sci & Informat Engn Tainan 70101 Taiwan

The purpose of a communication system is to transmit an information-bearing message signal through a channel that separates a transmitter from a receiver. The modulated carrier is often induced and interfered with by various noise sources. The co-channel separation system is a demodulation process function that operates at the same carrier modulation system. Here, we adopted the field-programmable gate array (FPGA) design platform configuration to develop, implement and achieve co-channel separation for an amplitude-locked loop demodulation chip-design digital system with additive white Gaussian noise interference. In this paper, the compact reconfigurable I/O built-in FPGA chip system is integrated and applied to obtain the cross-field relevant integration function for communication and chip-design system via programming in a graphical language. Additionally, the FPGA chip-design system runs all of the program code in hardware and provides high reliability and determinism. This cross-field ideal is adopted to save time and reduce complexity in the design development of a custom circuitry system. The FPGA chip-design system described in this paper is also used to achieve a digital communication chip prototype design model, followed by presentation of the steps necessary for building and program verification. The communication and chip-design concept may provide very useful physical applications for the industry.

关键词： Co-channel field-programmable gate array Additive white Gaussian noise Amplitude-locked loop LabVIEW Communication chip prototype design

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Design space exploration for sparse matrix-matrix multiplication on FPGAs

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INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS 2013年第2期41卷 205-219页

作者： Lin, Colin Yu Wong, Ngai So, Hayden Kwok-Hay Univ Hong Kong Dept Elect & Elect Engn Hong Kong Hong Kong Peoples R China

The design and implementation of a sparse matrix-matrix multiplication architecture on field-programmable gate arrays is presented. Performance of the design, in terms of computational latency, as well as the associated power-delay and energy-delay tradeoff are studied. Taking advantage of the sparsity of the input matrices, the proposed design allows user-tunable power-delay and energy-delay tradeoffs by employing different number of processing elements (PEs) in the architecture design and different block size in the blocking decomposition. Such ability allows designers to employ different on-chip computational architecture for different system power-delay and energy-delay requirements. It is in contrast to conventional dense matrix-matrix multiplication architectures that always favor the maximum number of PEs and largest block size. In our implementation, the better energy consumption and power-delay product favors less PEs and smaller block size for the 90%-sparsity matrix-matrix multiplications. Although in order to achieve better energy-delay product, more PEs and larger block size are preferred. Copyright (c) 2011 John Wiley & Sons, Ltd.

关键词： field-programmable gate array sparse sparse matrix-matrix multiplication design space exploration

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High-performance implementation of in-network traffic pacing for small-buffer networks

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COMPUTER COMMUNICATIONS 2013年第13期36卷 1450-1459页

作者： Hanay, Y. Sinan Dwaraki, Abhishek Hu, Kekai Wolf, Tilman NICT Ctr Informat & Neural Networks Osaka Japan Osaka Univ Adv Network Architecture Res Lab Osaka Japan Univ Massachusetts Dept Elect & Comp Engn Amherst MA 01003 USA

Demands on data communication networks continue to drive the need for increasingly faster link speeds. Optical packet switching networks promise to provide data rates that are sufficiently high to satisfy the needs of the future Internet core network. However, a key technological problem with optical packet switching is the very small size of packet buffers that can be implemented in the optical domain. Existing protocols, for example the widely used Transmission Control Protocol (TCP), do not perform well in such small-buffer networks. To address this problem, we have proposed techniques for actively pacing traffic at edge networks to ensure that traffic bursts are reduced or eliminated and thus do not cause packet losses in routers with small buffers. We have also shown that this traffic pacing can improve the performance of conventional networks that use small buffers (e.g., to reduce the cost of buffer memory on routers). A key challenge in this context is to develop systems that can perform such packet pacing efficiently and at high data rates. In this paper, we present the design and prototype of a hardware implementation of our packet pacing technique. We discuss and evaluate design trade-offs and present performance results from an prototype implementation based on a NetFPGA fieldprogrammable gate array system. Our results show that traffic pacing can be implemented with few hardware resources and without reducing system throughput. Therefore, we believe that traffic pacing can be deployed widely to improve the operation of current and future networks. (c) 2013 Elsevier B.V. All rights reserved.

关键词： Small-buffer network Traffic pacing Traffic burstiness field-programmable gate array Prototype

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Asynchronous Cellular Automaton-Based Neuron: Theoretical Analysis and On-FPGA Learning

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IEEE TRANSACTIONS ON NEURAL NETWORKS AND LEARNING SYSTEMS 2013年第5期24卷 736-748页

作者： Matsubara, Takashi Torikai, Hiroyuki Osaka Univ Grad Sch Engn Sci Osaka 5608531 Japan

A generalized asynchronous cellular automaton-based neuron model is a special kind of cellular automaton that is designed to mimic the nonlinear dynamics of neurons. The model can be implemented as an asynchronous sequential logic circuit and its control parameter is the pattern of wires among the circuit elements that is adjustable after implementation in a field-programmable gate array (FPGA) device. In this paper, a novel theoretical analysis method for the model is presented. Using this method, stabilities of neuron-like orbits and occurrence mechanisms of neuron-like bifurcations of the model are clarified theoretically. Also, a novel learning algorithm for the model is presented. An equivalent experiment shows that an FPGA-implemented learning algorithm enables an FPGA-implemented model to automatically reproduce typical nonlinear responses and occurrence mechanisms observed in biological and model neurons.

关键词： Asynchronous cellular automaton asynchronous sequential logic bifurcation phenomena field-programmable gate array neuron model nonlinear dynamics on-chip learning

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Development of plasma control system for divertor configuration on QUEST

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FUSION ENGINEERING AND DESIGN 2013年第6-8期88卷 1074-1077页

作者： Hasegawa, M. Nakamura, K. Zushi, H. Hanada, K. Fujisawa, A. Matsuoka, K. Mitarai, O. Idei, H. Nagashima, Y. Tokunaga, K. Kawasaki, S. Nakashima, H. Higashijima, A. Kyushu Univ Appl Mech Res Inst Kasuga Fukuoka 816 Japan Tokai Univ Toro Ku Kumamoto Japan

A plasma control system to sustain divertor configurations is developed on QUEST (Q-shu university experiment with steady-state spherical tokamak). Magnetic fluxes are numerically integrated at 100 kHz using FPGA (field-programmable gate array) modules and transferred to a main calculation loop at 4 kHz. With these signals, plasma shapes are identified in real time at 2 kHz under the assumption that the plasma current can be represented as one filament current. This calculation is done in another calculation loop in parallel by taking advantage of a multi-core processor of the plasma control system. The inside and outside plasma edge positions are controlled to their target positions using PID (proportional-integral-derivative) control loops. Whereas the outside edge position can not be controlled by the outer PF coil current, the inside edge position can be controlled by the inner PF coil current. (C) 2013 Elsevier B.V. All rights reserved.

关键词： Plasma shape identification Real-time control Divertor configuration field-programmable gate array

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The RF Amplifier Remote Monitoring System Based on Gigabit Ethernet

The RF Amplifier Remote Monitoring System Based on Gigabit E...

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4th International Conference on Manufacturing Science and Engineering (ICMSE 2013)

作者： Bao Jilong An Peng Ningbo Univ Technol Sch Elect & Informat Engn Ningbo 315016 Zhejiang Peoples R China

ISBN: (纸本)9783037856932

Based on the Gigabit Ethernet Protocol, the RF (Radio Frequency) power amplifier remote monitoring system was designed. The system collect digital signal from predistortion module, transmit the gigabit Ethernet network to outside, and improve the system efficiency. It adopts the SOPC technology hardcore and softcore, which makes the whole system realized in the single piece of chip. Softcore is the Altera's IF core-Nios II processor, design processors, make use of the custom parts and programs gigabit Ethernet transceiver and internal driving in processor. The integration and reliability of the system are in great improvement. Through testing, system function can satisfy transmission requirements of normal transceiver RF power amplifier state information and control information.

关键词： Power Amplifier Gigabyte Ethernet Remote Monitoring field-programmable gate array

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基于差分功率静噪算法的研究

基于差分功率静噪算法的研究

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2014年度全国无线及移动通信学术大会(WMC'14)

作者：张柱张英梅焦雪峰太原理工大学

通过分析现有井下对讲机中常用静噪算法,提出在低信噪比的情况下一种基于差分功率谱叠加的导频静噪算法的对讲机技术,并完成性能分析和F PGA实现。通过仿真和实测数据表明该算法具有可靠性高、运算复杂度低等优点。

关键词： Frequency Modulation 煤矿井下通信静噪开关差分功率谱 field-programmable gate array

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Automated Multi-Device Placement, I/O Voltage Supply Assignment, and Pin Assignment in Circuit Board Design

Automated Multi-Device Placement, I/O Voltage Supply Assignm...

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12th International Conference on field-programmable Technology (FPT)

作者： Seemuth, Daniel P. Morrow, Katherine Univ Wisconsin Madison WI 53706 USA

ISBN: (纸本)9781479921980;9781479921997

Embedded systems often contain many components, some with multiple field programmable gate arrays (FPGAs). Designing Printed Circuit Boards (PCBs) for these systems can be a complex process that is often tedious, error-prone, and time-intensive. Existing computer-aided design tools require designers to manually insert components and explicitly define the connections between every component on the PCB-a cumbersome process. A fast PCB design framework requiring reduced designer time and effort would be particularly advantageous for rapid prototyping and short production run PCBs. Therefore, this paper proposes a novel, freely-available open-source framework to capture design intent and automatically implement the design details. Designers express connectivity at a higher level of abstraction than enumerating or drawing each individual trace between components. Given the components and connection requirements, the proposed framework automatically generates component placements, I/O voltage supply assignments, and FPGA pin assignments to minimize trace length. We also propose a novel method to improve trace length estimations during placement, before FPGA pins have actually been assigned to those connections. The proposed framework quickly explores large solution spaces, enabling rapid prototyping and design space exploration, and can lead to lower costs in design time and other non-recurring expenses. We demonstrate that it produces favorable results for various design requirements, which suggests the framework will be especially appreciated by designers of systems with multiple FPGAs having large numbers of flexible pins.

关键词： printed circuit board design capture pin assignment field-programmable gate array high-level specification computer-aided design electronic design automation rapid prototyping

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A High Resolution FPGA-based Merged Delay Line TDC with Nonlinearity Calibration

A High Resolution FPGA-based Merged Delay Line TDC with Nonl...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Chen, Yuan-Ho Chung Yuan Christian Univ Dept Informat & Comp Engn Chungli Taiwan

ISBN: (纸本)9781467357623;9781467357609

This paper proposes a merged delay line (MDL) field-programmable gate array (FPGA) based time-to-digital converter (TDC). Instead of traditional tapped delay line (TDL), the proposed MDL-TDC merges several small delay cells to improve the linearity performance effectively. Implemented in a Xilinx XC5VLX110T-1FF1136 FPGA device, the proposed MDL-TDC has 5 0 ps time resolution, and the ranges of differential non-linearity (DNL) and integral non-linearity (INL) can be reduced 1 6 : 6 % and 5 : 4 % as compared with traditional one, respectively. Furthermore, 2 9 ps root-mean-square (RMS) is measured for the proposed MDL-TDC inputting a constant delay source. Therefore, the proposed MDL-TDC is recommended to implement in FPGA-based TDC achieving a high-resolution time and linearity performance.

关键词： Time-to-digital converter field-programmable gate array Differential non-linearity Merged delay line

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