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Proceedings of the ACM/SIGDA international symposium on field programmable gate arrays

作者： Jason H. Anderson University of Toronto Toronto ON Canada

ISBN: (纸本)9781605584102

Communications infrastructure, data processing and industrial electronics are the cornerstone application areas for programmable logic today. But what are the application domains of tomorrow? What nascent application areas could explode the growth of programmable logic usage and expand the programmable market? In this workshop, we will hear speakers from industry and academia talk about the emerging application areas for FPGAs and the challenges and opportunities in these areas. We will consider how programmable hardware and the associated tools should be enhanced to become better-suited to tomorrow's applications. The overarching aim of the workshop is to seed ideas in the research community by giving an applications perspective of the fertile topics for future research on FPGA architecture, CAD and applications.

关键词： high-performance computing field-programmable gate array applications performance power fpga reconfigurable computing

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QPACE: Quantum Chromodynamics Parallel Computing on the Cell Broadband Engine

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COMPUTING IN SCIENCE & ENGINEERING 2008年第6期10卷 46-54页

作者： Goldrian, Gottfried Huth, Thomas Krill, Benjamin Lauritsen, Jack Schick, Heiko Ouda, Ibrahim Heybrock, Simon Hierl, Dieter Maurer, Thilo Meyer, Nils Schaefer, Andreas Solbrig, Stefan Streuer, Thomas Wettig, Tilo Pleiter, Dirk Sulanke, Karl-Heinz Winter, Frank Simma, Hubert Schifano, Sebastiano Fabio Tripiccione, Raffaele Nobile, Andrea Drochner, Matthias Lippert, Thomas Fodor, Zoltan IBM Res & Dev Lab Boblingen Germany IBM Lab Boblingen Germany IBM Syst & Technol Grp Rochester MN USA IBM Lab Rochester MN USA Univ Regensburg D-8400 Regensburg Germany DESY Zeuthen Germany Univ Milan I-20122 Milan Italy Univ Ferrara I-44100 Ferrara Italy European Ctr Theoret Studies Trento Italy Res Ctr Julich Inst Adv Simulat Julich Germany Julich Supercomp Ctr Julich Germany Univ Wuppertal Wuppertal Germany

Application-driven computers for Lattice Gauge Theory simulations have often been based on system-on-chip designs, but the development costs can be prohibitive for academic project budgets. An alternative approach uses compute nodes based on a commercial processor tightly coupled to a custom-designed network processor. Preliminary analysis shows that this solution offers good performance, but it also entails several challenges, including those arising from the processor's multicore structure and from implementing the network processor on a field-programmable gate array.

关键词： field programmable gate arrays gauge field theory parallel machines quantum chromodynamics system-on-chip cell broadband engine field programmable gate array lattice gauge theory parallel computing system-on-chip designs QCD field-programmable gate array quantum chromodynamics chip scale packaging Network Processor String theory field programmable gate arrays parallel machines PARALLEL PROCESSING (COMPUTERS) system-on-chip Lattice gauge theory

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FPGA-based adaptive backstepping control system using RBFN for linear induction motor drive

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IET ELECTRIC POWER APPLICATIONS 2008年第6期2卷 325-340页

作者： Lin, F. -J. Teng, L. -T. Chen, C. -Y. Hung, Y. -C. Natl Cent Univ Dept Elect Engn Chungli 320 Taiwan Natl Dong Hwa Univ Dept Elect Engn Hualien 974 Taiwan

A field-programmable gate array (FPGA)-based adaptive backstepping control system with radial basis function network (RBFN) observer is proposed to control the mover position of a linear induction motor (LIM). First, the indirect. field-oriented mechanism is adopted for controlling the LIM. Next, a backstepping control law is designed step by step for the tracking control of periodic reference trajectories, in which the uncertainties are lumped by a conservative constant. However, the lumped uncertainty is unknown and difficult to obtain in advance in practical applications. Therefore an RBFN is derived to observe the lumped uncertainty in real-time, and an adaptive backstepping control system with RBFN observer is resulted. Then, an FPGA chip is adopted to implement the indirect. field-oriented mechanism and the developed control algorithms for possible low-cost, high-performance industrial applications. The effectiveness of the proposed control scheme is verified by some simulated and experimental results. By using the adaptive backstepping control system with RBFN observer, the FPGA-based LIM drive possesses the advantages of good transient control performance and robustness to uncertainties in the tracking of periodic reference trajectories.

关键词： induction motor drives radial basis function network periodic reference trajectory tracking radial basis function networks RBFN observer observers field-programmable gate array indirect field-oriented control lumped uncertainty neurocontrollers mover position control field programmable gate arrays linear induction motor drive adaptive control linear induction motors FPGA machine vector control adaptive backstepping control position control transient control performance

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High-Speed Real-Time Simulation for Power Electronic Systems

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SIMULATION-TRANSACTIONS OF THE SOCIETY FOR MODELING AND SIMULATION INTERNATIONAL 2008年第8-9期84卷 441-456页

作者： Word, Dale Bednar, Richard Zenor, John J. Hingorani, Nari G. Calif State Univ Chico Dept Elect & Comp Engn Chico CA 95929 USA Calif State Univ Chico McLeod Inst Simulat Sci Chico CA 95929 USA Independent Consultant Los Altos Hills CA 94022 USA

Real-time simulators have been used as an aid to power system design for many years. Over time, scaled-down physical models and analog computer-based simulators have given way to real-time simulators based on digital technology. Another trend has been the need for shorter and shorter frame times for these digital real-time simulators. Modern power electronic systems use high-frequency Pulse-Width Modulated (PWM) controllers. Indications are that frame times of 2 mu S are needed for PWM switching frequencies of 10 KHz. As frequencies increase further it is possible that frame times of less than 1 mu S may be required. In order to achieve these very short frame times, the implementation of this type of simulator requires careful selection of the methods and technologies used. The first involves thorough analysis of the integration method chosen, to ensure that it provides the performance, stability and accuracy required. Additionally, the choice of computing platform is crucial to provide the computational support to meet these very aggressive timing requirements.

关键词： simulation power electronics real-time Digital Signal Processors field-programmable gate array

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Application-specific processor architecture: Then and now

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JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2008年第1-2期53卷 197-215页

作者： Cappello, Peter Univ Calif Santa Barbara Dept Comp Sci Santa Barbara CA 93106 USA

We first relate the architecture of systolic arrays to the technological and economic design forces acting on architects of special-purpose systems some 20 years ago. We then observe that those same design forces now are bearing down on the architects of contemporary general-purpose processors, who consequently are producing general-purpose processors whose architectural features are increasingly similar to those of systolic arrays. We then describe some economic and technological forces that are changing the landscape of architectural research. At base, they are the increasing complexity of technology and applications, the fragmenting of the general-purpose processor market, and the judicious use hardware configurability. We describe a 2D architectural taxonomy, identifying what, we believe, to be a "sweet spot" for architectural research.

关键词： application-specific processor computer architecture field-programmable gate array FPGA general-purpose processor processor array systolic array taxonomy

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Application-specific processor architecture: Then and now

Application-specific processor architecture: Then and now

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17th IEEE International Conference on Application-Specific Systems, Architectures and Processors

作者： Cappello, Peter Univ Calif Santa Barbara Dept Comp Sci Santa Barbara CA 93106 USA

关键词： application-specific processor computer architecture field-programmable gate array FPGA general-purpose processor processor array systolic array taxonomy

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FPGA-oriented HW/SW implementation of the MPEG-4 video decoder

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MICROPROCESSORS AND MICROSYSTEMS 2007年第5期31卷 313-325页

作者： Zemva, Andrej Verderber, Matjaz Univ Ljubljana Fac Elect Engn Ljubljana 1000 Slovenia

This paper presents an FPGA-oriented implementation methodology for the MPEG-4 video decoder based on a hardware/software co-design approach. The MPEG-4 decoder is based on MoMuSys optimized reference software combined with new hardware VLSI architectures. New architectures for input demultiplexing, variable length decoding and inverse discrete cosine transform are developed. All software and hardware structures are evaluated in terms of visual quality, computational complexity and memory bandwidth metrics. The presented implementation is compared with an optimized reference software-based solution. Simulation results demonstrate a reduction of decoder complexity, especially speed and memory bandwidth, while maintaining an acceptable quality of decoded sequences. The proposed hardware additions provide 30% speed improvement over software solution, thereby reducing the clock rate required to process full-rate video from 300 MHz down to 213 MHz. The MPEG-4 decoder was functionally tested on a Flextronics FPGA prototyping board. (c) 2006 Elsevier B.V. All rights reserved.

关键词： MPEG-4 decoder field-programmable gate array hardware very large scale integration co-design

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Using FPGA devices to accelerate biomolecular simulations

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COMPUTER 2007年第3期40卷 66-+页

作者： Alam, Sadaf R. Agarwal, Pratul K. Smith, Melissa C. Vetter, Jeffrey S. Caliga, David Oak Ridge Natl Lab Comp Sci & Math Div Future Technol Grp Oak Ridge TN 37831 USA Oak Ridge Natl Lab Computat Biol Inst Oak Ridge TN 37831 USA Oak Ridge Natl Lab Engn Sci & Technol Div Oak Ridge TN 37831 USA

A field-programmable gate array implementation of a molecular dynamics simulation method reduces the microprocessor time-to-solution by a factor of three while using only high-level languages. The application speedup on FPGA devices increases with the problem size. The authors use a performance model to analyze the potential of simulating large-scale biological systems faster than many cluster-based supercomputing platforms.

关键词： biology computing field programmable gate arrays high level languages microprocessor chips molecular biophysics FPGA device biomolecular simulation cluster-basedsupercomputing platform field-programmable gate array high-level language large-scale biolog

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FPGA-based real-time 3D image preprocessing for image-guided medical interventions

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JOURNAL OF REAL-TIME IMAGE PROCESSING 2007年第4期1卷 285-301页

作者： Dandekar, Omkar Castro-Pareja, Carlos Shekhar, Raj Univ Maryland Dept Diagnost Radiol & Nucl Med Baltimore MD 21201 USA Univ Maryland Dept Elect & Comp Engn College Pk MD 20742 USA

Minimally invasive image-guided interventions (IGIs) are time and cost efficient, minimize unintended damage to healthy tissue, and lead to faster patient recovery. One emerging trend in IGI workflow is to use volumetric imaging modalities such as low-dose computed tomography (CT) and 3D ultrasound to provide real-time, accurate anatomical information intraoperatively. These intraoperative images, however, are often characterized by quantum (in low-dose CT) or speckle (in ultrasound) noise and must be enhanced prior to any advanced image processing. Anisotropic diffusion filtering and median filtering have been shown to be effective in enhancing and improving the visual quality of these images. However, achieving real-time performance, as required by IGIs, using software-only implementations is challenging because of the sheer size of the images and the arithmetic complexity of the filtering operations. We present a field-programmable gate array-based reconfigurable architecture for real-time preprocessing of intraoperative 3D images. The proposed architecture provides programmable kernels for 3D anisotropic diffusion filtering and 3D median filtering within the same framework. The implementation of this architecture using an Altera Stratix-II device achieved a voxel processing rate close to 200 MHz, which enables the use of these processing techniques in the IGI workflow prior to advanced operations such as segmentation, registration, and visualization.

关键词： Image-guided interventions 3D anisotropic diffusion 3D median filtering Real-time image processing field-programmable gate array

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A genetic algorithm high-level optimizer for complex datapath and data-flow digital systems

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APPLIED SOFT COMPUTING 2007年第3期7卷 979-994页

作者： Salcic, Zoran Coghill, George Maunder, Bruce Univ Auckland Dept Elect & Comp Engn Auckland New Zealand

In this paper we present a methodology for optimizing complex datapath oriented digital circuits. An optimizer was developed based on the earlier development of an automatic circuit synthesizer that synthesizes hardware description language specifications based on available functional modules. A genetic algorithm is tailored to the problem of digital circuit optimization through the development of specific structures and procedures. In particular, a concise encoding of the circuit is developed that the genetic algorithm can manipulate. Specific crossover and mutation mechanisms are also developed to complement the functionality of the synthesizer. The searches are effected by altering module data type, hardware resource sharing, and module implementation version. A fitness function is derived that makes use of a number of optimization parameters to objectively evaluate each particular circuit. The features of each circuit are calculated and estimated during the analysis phase. (c) 2006 Elsevier B. V. All rights reserved.

关键词： optimization data-flow genetic algorithm high-level synthesis field-programmable gate array

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