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An enhanced constant sample-time digital tachometer through oversampling

TRANSACTIONS OF THE INSTITUTE OF MEASUREMENT AND CONTROL 2004年第2期26卷 83-98页

作者： Kavanagh, RC Natl Univ Ireland Univ Coll Cork Dept Elect & Elect Engn Mechatron Res Lab Cork Ireland

High-quality digital tachometers are incorporated into servo, mechatronic, robotic and precision production systems for the calculation of accurate, high-bandwidth, digital velocity information. The M/T-type tachometer and the related constant sample-time digital tachometer (CSDT) have been shown to perform well in many such systems. However, sensor nonideality can introduce very significant errors into the tachometer output. In this paper, it is shown that performance can be greatly improved (i.e., the noise present in the velocity signal significantly reduced) by oversampling the counter values used for velocity calculation. The counting and oversampling operations inherent to the oversampled CSDT (OCSDT) are implemented using a field-programmable gate array (FPGA). The design of the digital circuitry is described in detail, with particular emphasis on the circuits required for implementation and control of the oversampling operation. The FPGA acts as a peripheral device to a digital signal processor (DSP). Besides implementing some division-based calculations to generate a velocity word, the DSP can carry out other measurement and control functions, as required by the overall system. Simulation studies and experimental results are used to highlight the advantages of the oversampling technique.

关键词： digital tachometer field-programmable gate array FPGA oversampling servo system shaft encoder velocity measurement

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FPGA implementation of population-based ant colony optimization

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APPLIED SOFT COMPUTING 2004年第3期4卷 303-322页

作者： Scheuermann, B So, K Guntsch, M Middendorf, M Diessel, O ElGindy, H Schmeck, H Univ Karlsruhe TH Inst AIFB Karlsruhe Germany Univ New S Wales Kensington NSW 2033 Australia Univ Leipzig Inst Comp Sci Leipzig Germany

We present a hardware implementation of population-based ant colony optimization (P-ACO) on field-programmable gate arrays (FPGAs). The ant colony optimization meta-heuristic is adopted from the natural foraging behavior of real ants and has been used to find good solutions to a wide spectrum of combinatorial optimization problems. We describe the P-ACO algorithm and present a circuit architecture that facilitates efficient FPGA implementations. The proposed design shows modest space requirements but leads to a significant reduction in runtime over software-based solutions. Several modifications and extensions of the basic algorithm are also presented, including the approximation of the heuristic function by a small, dynamically changing set of favorable decisions. (C) 2004 Elsevier B.V. All rights reserved.

关键词： ant colony optimization ant algorithm field-programmable gate array FPGA

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Application-specific bridging fault testing of FPGAs

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JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS 2004年第3期20卷 279-289页

作者： Tahoori, MB Northeastern Univ Dept ECE Boston MA 02115 USA

In this paper, a new technique for testing the interconnects of any arbitrary design mapped into an FPGA is presented. In this technique, only the configuration of logic blocks used in the design is changed, and the structure of the design remains unchanged. The test vector and configuration generation problem is systematically converted to a Boolean satisfiability (SAT) problem, and state of the art SAT-solvers are exploited for test vector and configuration generation. Experimental results on various benchmark circuits show that only two test configurations are required to test for all bridging faults, achieving 100% fault coverage, with respect to the fault list. Moreover, test vector and configuration generation time is less than a second for all benchmark designs.

关键词： field-programmable gate array interconnect satisfiability bridging fault

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Highly configurable platforms for embedded computing systems

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MICROELECTRONICS JOURNAL 2003年第11期34卷 1025-1029页

作者： Vahid, F Lysecky, R Zhang, CJ Stitt, G Univ Calif Riverside Dept Comp Engn & Sci Riverside CA 92521 USA Univ Calif Riverside Dept Elect Engn Riverside CA 92521 USA

Platform chips, which are pre-designed chips possessing numerous processors, memories, coprocessors, and field-programmable gates arrays, are becoming increasingly popular. Platforms eliminate the costs and risks associated with creating customized chips, but with the drawbacks of poorer performance and energy consumption. Making platforms highly configurable, so they can be tuned to the particular applications that will execute on those platforms, can help reduce those drawbacks. We discuss the trends leading embedded system designers towards the use of platforrns instead of customized chips. We discuss UCR research in designing highly configurable platforms, highlighting some of our work in highly configurable caches, and in hardware/software partitioning. (C) 2003 Elsevier Ltd. All rights reserved.

关键词： platform system-on-a-chip configurable field-programmable gate array cores embedded systems low energy cache hardware/software partitioning architecture tuning

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Setting the PACE in IRSP: A reconfigurable PC-based array control electronics system for infrared scene projection

Setting the PACE in IRSP: A reconfigurable PC-based array co...

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Conference on Technologies for Synthetic Environments - Hardware-in-the-Loop Testing VIII

作者： Goldsmith, GC Herald, WL Erickson, RA Irvine, WS Mackin, PR Bryant, P Lindberg, B USAF Res Lab Munit Directorate Eglin AFB FL 32542 USA

ISBN: (纸本)0819449520

The development of a new generation PC-based array control electronics (PACE) system was completed during the first quarter of 2003 in the Kinetic Kill Vehicle Hardware-in-the-loop (KHILS) facility. This system replaces the bulky VME-based system that was the previous standard with more compact digital control electronics using field-programmable gate array (FPGA) technology hosted on a personal computer. The analog interface electronics (AIE) were redesigned to eliminate obsolete components and miniaturize the package for better compatibility with harsh environments. The resulting PACE system supports both Santa Barbara Infrared Inc. (SBIR) and Honeywell Technology Center's (HTC's) 512 x 512 legacy emitter array infrared projection devices as well as SBIR's upcoming 1024 x 1024 and next-generation 512 x 512 arrays. Two FPGA-based PCI boards enable this system to reconfigure the inputs, processing and outputs of the projection electronics through firmware loaded from the control PC. The increased flexibility provides potential for additional real-time functions such as distortion correction, convolution and calibration to be implemented along with nonuniformity correction (NLJC) techniques by simply reconfiguring firmware. This paper describes the capabilities of the new PACE system in terms of current and future hardware-in-the-loop (HITL) requirements.

关键词： infrared projector emitter arrays field-programmable gate array real-time processing nonuniformity correction

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Performance-driven placement for dynamically reconfigurable FPGAs

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ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS 2002年第4期7卷 628-642页

作者： Wu, GM Lin, JM Chang, YW Han Hua Univ Dept Informat Management Dalin Chiayi 22 Taiwan Realtek Semicond Corp Hsinchu Taiwan Natl Taiwan Univ Dept Elect Engn Taipei 10764 Taiwan

In this article, we introduce a new placement problem motivated by the Dynamically Reconfigurable FPGA (DRFPGA) architectures. Unlike traditional placement, the problem for DRFPGAs must consider the precedence constraints among logic components. For the placement, we develop an effective metric that can consider wirelength, register requirement, and power consumption simultaneously. With the considerations of the new metric and the precedence constraints, we then present a three-stage scheme of partitioning, initial placement generation, and placement refinement to solve the new placement problem. Experimental results show that our placement scheme with the new metric achieves respective improvements of 17.2, 27.0, and 35.9% in wirelength, the number of registers, and power consumption requirements, compared with the list scheduling method.

关键词： algorithms design experimentation measurement performance computer-aided design of VLSI dynamically reconfigurable layout placement field-programmable gate array

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Alternatives in FPGA-based SAD implementations 1

Alternatives in FPGA-based SAD implementations

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IEEE International Conference on field-programmable Technology (FPT)

作者： Wong, S Stougie, B Cotofana, S Delft Univ Technol Comp Engn Lab Delft Netherlands

ISBN: (纸本)0780375742

In multimedia processing, it is well-known that the sum-of-absolute-differences (SAD) operation is the most time-consuming operation when implemented in software running on programmable processor cores. This is mainly due to the sequential characteristic of such an implementation. In this paper, we investigate several hardware implementations of the SAD operation and map the most promising one in FPGA. Our investigation shows that an adder tree based approach yields the best results in terms of speed and area requirements and has been implemented as such by writing high-level VHDL code. The design was functionally verified by utilizing the MAX+plus II 10.1 Baseline software package from Altera Corp. and then synthesized by utilizing the LeonardoSpectrum software package from Exemplar Logic Inc. Preliminary results show that the design can be clocked at 380 Mhz. This result translates into a faster than real-time full search in motion estimation for the main profile/main level of the MPEG-2 standard.

关键词： sum of absolute difference field-programmable gate array hardware synthesis

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Floating-point ADC optimized for acquisition of deterministic signals

Floating-point ADC optimized for acquisition of deterministi...

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19th IEEE Instrumentation and Measurement Technology Conference (IMTC/2002)

作者： Groza, V Univ Ottawa Sch Informat Technol & Engn Ottawa ON K1N 6N5 Canada

ISBN: (纸本)0780372182

This paper presents a high-speed floating-point analog-to-digital converter in the framework of deterministic signal acquisition systems. The proposed circuit allows quantization of large dynamics signals, while keeping a low relative error. FP-ADC precision characteristics are analyzed In the context of exponential decay signals acquisition.

关键词： floating-point analog-to-digital converter field-programmable gate array error analysis

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A fixed-point phase lock loop in a software defined radio

A fixed-point phase lock loop in a software defined radio

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作者： Johannes, Michael T. Naval Postgraduate School

学位级别：硕士

A software defined radio is a much more flexible platform than traditional, hardware implemented radios. By implementing radio functions in software, and putting those functions on a field programmable gate array (FPGA) chip, users will have the ability to download mission specific radio capabilities. This thesis examines a fundamental piece of the receiver, the Phase-Lock Loop (PLL), simulates a software PLL, and investigates the effects of fixed-point versus floating point mathematics required for an FPGA based PLL. With a fixed-point PLL simulator, figures of merit such as lock-time, lock range, and pull-in range are determined for typical signal-to-noise ratio (SNR) levels.

关键词： software radio fixed-point phase lock loop field-programmable gate array

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The design of an evolvable coprocessor environment

The design of an evolvable coprocessor environment

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18th IEEE Instrumentation and Measurement Technology Conference (IMTC/2001)

作者： Abielmona, R Groza, V Univ Ottawa Sch Informat Technol Engn Ottawa ON K1N 6N5 Canada

In this paper we propose a design based on a genetic algorithm to evolve the logic circuit of a defined input function, in which we aim to minimize the total number of gates used. Our design is outlined and briefly di... 详细信息

ISBN: (纸本)0780366468

关键词： genetic algorithm field-programmable gate array evolvable hardware

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