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Wearable sensor-based measurement and classification of athletic activities using FPGA and EdgeTPU

PROCEEDINGS OF THE INSTITUTION OF MECHANICAL ENGINEERS PART P-JOURNAL OF SPORTS ENGINEERING AND TECHNOLOGY 2025年

作者： Muralikrishnan, P. Maheswari, M. K Ramakrishnan Coll Engn Samayapuram Kariyamanickam Rd Tiruchirappalli 621112 Tamil Nadu India

Wearable sensors, such as smartwatches, often face challenges in providing accurate readings due to variations in sensor quality and placement irregularities. Furthermore, deep convolutional neural networks (CNNs) can be resource-intensive, making them less suitable for real-time applications in wearable technology. This study introduces a novel approach utilizing Edge Tensor Processing Units (EdgeTPUs) combined with field-programmable gate arrays (FPGAs) for activity classification in athletes, specifically designed for resource-constrained environments. EdgeTPU models are optimized for low memory usage and high computational efficiency, making them ideal for microcontrollers used in wearable devices. To address model size and complexity, we employ quantization techniques and a lightweight neural network design. Experiments using the UCI-HAR, WISDM, and WEAR datasets show that our approach achieves a classification accuracy of 98.97%. The FPGA implementation offers high throughput and low latency, critical for real-time processing in wearable sensors. Additionally, we present three innovative approaches for complex loop optimization to enhance convolution efficiency. With a usage rate of 24.6%, the EdgeTPU model implemented on a Virtex-7 FPGA demonstrates effective hardware utilization. Our results indicate that the integration of FPGA and EdgeTPU technologies enables efficient real-time monitoring of athletic activities in wearable devices with limited resources.

关键词： Edge tensor processing unit athletic activities field-programmable gate array FPGA implementation signal classification

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Dual threshold input receiver FPGA-only signal digitization method for time-of-flight positron emission tomography

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BIOMEDICAL ENGINEERING LETTERS 2024年第4期14卷 847-858页

作者： Ko, Guen Bae Lee, Jae Sung Brightonix Imaging Inc Seoul 04782 South Korea Seoul Natl Univ Inst Radiat Med Med Res Ctr Seoul 03080 South Korea Seoul Natl Univ Coll Med Dept Nucl Med Seoul 03080 South Korea Seoul Natl Univ Coll Engn Interdisciplinary Program Bioengn Seoul 03080 South Korea

As silicon photomultiplier (SiPM)-based time-of-flight (TOF) positron emission tomography (PET) becomes popular, the need for sophisticated PET data acquisition (DAQ) systems is increasing. One promising solution to this challenge is the adoption of a field-programmable gate array (FPGA)-only signal digitization method. In this paper, we propose a new approach to efficiently implement an FPGA-only digitizer. We configured the input/output (IO) port of the FPGA to function as a dual-threshold voltage comparator through the use of simple passive circuitry and heterogeneous IO standards. This configuration overcomes the limitations of existing methods by allowing different threshold voltages for adjacent IO pins, effectively reducing routing complexity and lowering manufacturing costs. An FPGA-only digitizer was implemented by integrating the dual-threshold voltage comparator and FPGA-based time-to-digital converter. By combining the dual-threshold time-over-threshold (TOT) method and curve fitting, precise energy information could be obtained. The performance of the FPGA-only digitizer was assessed using a detector setup comprising a 3 x 3 x 20 mm3 LYSO scintillation crystal and a single pixel SiPM. Using the configured evaluation setup, an energy resolution of 12.5% and a time resolution of 146 +/- 9 ps were achieved for a 20 mm scintillation crystal. The dual-threshold TOT implemented using the proposed method showed consistent linearity across an energy range of 100 keV to 600 keV. The proposed method is well-suited for the development of cost-effective DAQ systems in highly integrated TOF PET systems.

关键词： Positron emission tomography field-programmable gate array Silicon photomultiplier Time-to-digital converter Time-over-threshold

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FPGA-Based Implementation of Real-Time Cardiologist-Level Arrhythmia Detection and Classification in Electrocardiograms Using Novel Deep Learning

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INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS 2024年第0期

作者： Chandrasekaran, Saravanakumar Chandran, Srinivasan Selvam, Immaculate Joy SRM Valliammai Engn Coll ECE Chennai Tamil Nadu India Rajalakshmi Engn Coll EEE Chennai Tamil Nadu India Saveetha Engn Coll ECE Chennai Tamil Nadu India

Cardiac arrhythmia refers to irregular heartbeats caused by anomalies in electrical transmission in the heart muscle, and it is an important threat to cardiovascular health. Conventional monitoring and diagnosis still depend on the laborious visual examination of electrocardiogram (ECG) devices, even though ECG signals are dynamic and complex. This paper discusses the need for an automated system to assist clinicians in efficiently recognizing arrhythmias. The existing machine-learning (ML) algorithms have extensive training cycles and require manual feature selection;to eliminate this, we present a novel deep learning (DL) architecture. Our research introduces a novel approach to ECG classification by combining the vision transformer (ViT) and the capsule network (CapsNet) into a hybrid model named ViT-Cap. We conduct necessary preprocessing operations, including noise removal and signal-to-image conversion using short-time Fourier transform (SIFT) and continuous wavelet transform (CWT) algorithms, on both normal and abnormal ECG data obtained from the MIT-BIH database. The proposed model intelligently focuses on crucial features by leveraging global and local attention to explore spectrogram and scalogram image data. Initially, the model divides the images into smaller patches and linearly embeds each patch. Features are then extracted using a transformer encoder, followed by classification using the capsule module with feature vectors from the ViT module. Comparisons with existing conventional models show that our proposed model outperforms the original ViT and CapsNet in terms of classification accuracy for both binary and multi-class ECG classification. The experimental findings demonstrate an accuracy of 99% on both scalogram and spectrogram images. Comparative analysis with state-of-the-art methodologies confirms the superiority of our framework. Additionally, we configure a field-programmable gate array (FPGA) to implement the proposed model for real-time ar

关键词： accuracy arrhythmia capsule network deep learning electrocardiogram field-programmable gate array power processing time vision transformer

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Converter Topology for Megawatt Scale Applications With Reduced Filtering Requirements, Formed of IGBT Bridge Operating in the 1000 Hz Region With Parallel Part-Rated High-Frequency SiC MOSFET Bridge

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IEEE TRANSACTIONS ON POWER ELECTRONICS 2024年第1期39卷 799-813页

作者： Li, Ning Macavilca, Marlee Basurto Wu, Chenqi Finney, Stephen Judge, Paul D. Univ Edinburgh Sch Engn Inst Energy Syst Edinburgh EH9 3JL Midlothian Scotland

This article investigates the design and control of the parallel-hybrid converter (PHC), which consists of parallel connection of a silicon insulated gate bipolar transistor (IGBT) bridge and a partially rated silicon carbide (SiC) MOSFETs bridge with a shared dc bus. The IGBT bridge processes the bulk of the power, while switching at a low frequency to maximize efficiency, while the SiC MOSFETs bridge's lower relative switching loss is exploited to filter low-order harmonics from the IGBT bridge. A finite-set model predictive controller is detailed that allows IGBT switching frequencies down to 1 kHz to be achieved while also tightly controlling the magnitude of current in the SiC bridge. A genetic algorithm is utilized to automatically tune the control and investigate the design of the output filter as well as the influence of the controller time-step and horizon length on the performance. Power loss estimates of a 1.5MWapplication case are made showing potential for significant power-loss reductions. Experimental tests validate an field-programmable gate array (FPGA) implementation of the controller and topologies performance, with IGBT bridge frequencies below 1.2 kHz and grid-current total harmonic distortion below 3% achieved. The ability of converter to switch operation between a high-current and a low-current mode and dynamic performance is also verified.

关键词： Active filtering depth-first search (DFS) field-programmable gate array model predictive control partial load efficiency power electronic converter silicon carbide (SiC) MOSFETs

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FPGA-based performance evaluation of backstepping control and computed torque control for industrial robots

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INTERNATIONAL JOURNAL OF AUTOMATION AND CONTROL 2025年第1期19卷 101-132页

作者： Fekik, Arezki Khati, Hocine Azar, Ahmad Taher Hamida, Mohamed Lamine Denoun, Hakim Kamal, Nashwa Ahmad Univ Akli Mohand Oulhadj Bouria Dept Elect Engn Rue Drissi Yahia Bouira 10000 Algeria Nantes Univ Ecole Cent Nantes CNRS LS2NUMR 6004 F-44000 Nantes France Univ Mouloud Mammeri Tizi Ouzou Fac Elect & Comp Engn Dept Automat Design & Drive Prod Syst Lab Tizi Algeria Prince Sultan Univ Coll Comp & Informat Sci Riyadh 11586 Saudi Arabia Prince Sultan Univ Automated Syst & Soft Comp Lab ASSCL Riyadh Saudi Arabia Benha Univ Fac Comp & Artificial Intelligence Banha 13518 Egypt Elect Engn Adv Technol Lab LATAGE Tizi Algeria Cairo Univ Fac Engn Giza 12613 Egypt

In this paper, a comparative study is conducted on two nonlinear control techniques: state feedback control through backstepping and computed torque control. The study focuses on their application to the industrial robot PUMA 560. The primary goal is to assess the trajectory tracking accuracy and speed achieved by these methods. To achieve this objective, both control techniques are employed on the Zed board Zynq FPGA platform, encompassing both simulation and hardware systems. Subsequently, the experimental results are thoroughly analysed and compared, aiming to accentuate the unique advantages and constraints associated with each method.

关键词： field-programmable gate array FPGA backstepping control computed torque control CTC Zed board Zynq PUMA 560

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Design for High-Precision Time-Sensitive Networking: Synchronization for the Quantum Network Control Plane

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IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS 2024年第7期42卷 1861-1870页

作者： Bush, Stephen F. Iversen, Christopher G. Challener, William A. Gen Elect Res Niskayuna NY 12309 USA ForwardEdge ASIC St Paul MN 55108 USA Gen Elect Res Ctr Niskayuna NY 12309 USA

Tight integration between classical and quantum networking requires strict synchronization of events between the classical and quantum portions of the network. Time-Sensitive Networking (TSN) as defined by IEEE 802.1Q is limited to accuracy on the order of microseconds due to limitations in time synchronization performance;TSN gate control is thus similarly limited. This work presents a new High-Precision TSN that enables greater accuracy and resolution toward sub-nanosecond TSN gate control and can directly support entanglement distribution, a key component in a software-designed quantum network architecture where classical control can reach deep into the quantum network and directly control time critical operations.

关键词： Photonics Quantum networks Detectors Synchronization Quantum entanglement Logic gates Real-time systems Control plane field-programmable gate array network management quantum channels quantum communication quantum networks quantum network architecture quantum optics real-time control real-time systems software-defined network timing synchronization time-sensitive network

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ION-FAST as the NIRFI's Ionospheric Diagnostic Platform

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ATMOSPHERE 2024年第2期15卷 188页

作者： Moiseev, Sergey P. Shindin, Alexei V. Grekhneva, Kseniya K. Pavlova, Viktoriya A. Timukin, Nikita S. Lobachevsky State Univ Nizhni Novgorod Radiophys Res Inst Bolshaya Pecherskaya St 25-12a Nizhnii Novgorod 603950 Russia

In December 2021, we presented a prototype of a fast ionosonde for vertical sounding based on the usage of publicly available radio-electronic components. This approach led to a major reduction in the cost of the created device. We called our development ION-FAST, which characterizes the key feature of the ionosonde: the possibility of continuous operation at a speed of one ionogram per second, which is required to study the rapid processes of redistribution of the electron concentration during heating experiments. In May 2022, an ionosonde for vertical sounding of the ionosphere, developed at the Radiophysical Research Institute of Nizhni Novgorod (NIRFI), was put into continuous operation at the SURA facility. This report provides a description of the improvements made to the prototype over the last year and the path to be passed from idea to implementation. The results of the first months of the prototype's operation (especially the results of the supporting optic experiment in August 2022), as well as prospects for further use and modernization, are provided. In addition, the realization of the oblique chirp-sounding receiver prototype as an extension of the proposed diagnostic platform's functionality, including the first results, is presented.

关键词： ionosonde ionosphere field-programmable gate array software-defined radio vertical sounding oblique sounding ionogram

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Fully parallel low-density parity-check code-based polar decoder architecture for 5G wireless communications

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ETRI JOURNAL 2024年第3期46卷 485-500页

作者： Devadoss, Dinesh Kumar Ramapackiam, Shantha Selvakumari Mepco Schlenk Engn Coll Dept Elect & Commun Engn Sivakasi India

A hardware architecture is presented to decode (N, K) polar codes based on a low-density parity-check code-like decoding method. By applying suitable pruning techniques to the dense graph of the polar code, the decoder architectures are optimized using fewer check nodes (CN) and variable nodes (VN). Pipelining is introduced in the CN and VN architectures, reducing the critical path delay. Latency is reduced further by a fully parallelized, single-stage architecture compared with the log N stages in the conventional belief propagation (BP) decoder. The designed decoder for short-to-intermediate code lengths was implemented using the Virtex-7 field-programmable gate array (FPGA). It achieved a throughput of 2.44 Gbps, which is four times and 1.4 times higher than those of the fast-simplified successive cancellation and combinational decoders, respectively. The proposed decoder for the (1024, 512) polar code yielded a negligible bit error rate of 10-4 at 2.7 Eb/No (dB). It converged faster than the BP decoding scheme on a dense parity-check matrix. Moreover, the proposed decoder is also implemented using the Xilinx ultra-scale FPGA and verified with the fifth generation new radio physical downlink control channel specification. The superior error-correcting performance and better hardware efficiency makes our decoder a suitable alternative to the successive cancellation list decoders used in 5G wireless communication.

关键词： 5G new radio belief propagation field-programmable gate array low-density parity-check code pipeline polar code

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Scalable On-Chip Optoelectronic Ising Machine Utilizing Thin-Film Lithium Niobate Photonics

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ACS PHOTONICS 2024年第4期11卷 1703-1714页

作者： Li, Zhenhua Gan, Ranfeng Chen, Zihao Deng, Zhaoang Gao, Ran Chen, Kaixuan Guo, Changjian Zhang, Yanfeng Liu, Liu Yu, Siyuan Liu, Jie Sun Yat Sen Univ Sch Elect & Informat Technol State Key Lab Optoelect Mat & Technol Guangzhou 510006 Peoples R China Beijing Inst Technol Sch Informat & Elect Beijing 100081 Peoples R China South China Normal Univ South China Acad Adv Optoelect Guangdong Prov Key Lab Opt Informat Mat & Technol Guangzhou 510006 Peoples R China Hefei Natl Lab Hefei 230088 Peoples R China Zhejiang Univ Coll Opt Sci & Engn Int Res Ctr Adv Photon State Key Lab Extreme Photon & Instrumentat Hangzhou 310058 Peoples R China Zhejiang Univ Jiaxing Res Inst Intelligent Opt & Photon Res Ctr Jiaxing Key Lab Photon Sensing & Intelligent Imagi Jiaxing 314000 Peoples R China

The Ising machine (IM) has emerged as a promising tool for tackling nondeterministic polynomial-time hard combinatorial optimization problems in real-world applications. Among various types of IMs, optoelectronic IMs based on electro-optical (EO) modulators stand out as an impressive platform for Ising computations. They offer a simple and stable architecture, with the EO modulator providing a natural inline nonlinear transfer function for the Ising model. However, integrated optoelectronic IMs have not been demonstrated until now, and exploring large-scale computations within the constraints of digital hardware resources remains an open challenge for these systems. In this paper, an integrated optoelectronic IM based on a thin-film lithium niobate (TFLN) photonic chip is presented, in conjunction with a sparse matrix-vector multiplication algorithm embedded in a field-programmable gate array that optimizes hardware resource utilization and minimizes computational latency. This setup allows us to solve multiple types of MAX-CUT problems with up to 2048 spins and achieve a remarkably low iteration latency of 1.78 mu s. To further address the constraints posed by digital devices when tackling larger-scale Ising problems, we extend the application of the TFLN chip to yet another new scheme in which the single, compact on-chip modulator concurrently performs operations of linear multiplication and nonlinear transformation. This scheme demonstrates the capability to address large-scale MAX-CUT problems involving up to 16,384 spins, which, to the best of our knowledge, are the largest-scale problems solved on an on-chip IM, highlighting its potential to overcome digital limitations. The TFLN-based optoelectronic IMs provide a compact solution with high scalability for potentially practical applications in addressing complex combinatorial optimization problems.

关键词： Ising machine optical computing thin-filmlithium niobate field-programmable gate array matrix-vector multiplication nonlinear operation

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High-speed, low-power, and configurable on-chip training acceleration platform for spiking neural networks

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APPLIED INTELLIGENCE 2024年第20期54卷 9655-9670页

作者： Liu, Yijun Xu, Yujie Ye, Wujian Cui, Youfeng Zhang, Boning Lin, Wenjie Guangdong Univ Technol Sch Integrated Circuits Guangzhou 510000 Guangdong Peoples R China

Spike timing-dependent plasticity (STDP) is crucial for training neural networks (SNNs), offering a hardware-compatible and energy-efficient alternative to backpropagation. Current STDP hardware platforms encounter significant challenges, such as slowness, high energy consumption, and limited configurability. To overcome these issues, this paper presents a high-performance SNN training platform. A parallel multi-ring first-in-first-out structure with event-driven processing for spike handling is proposed, which enhances training efficiency, and the flexible pre- and post-synaptic parallelism enhances speed and flexibility. A dataflow strategy that considers spike sparsity unifies spike representations by updating weights only upon spike arrival, thereby promoting logical symmetry and enabling parallelization. Additionally, three encoding strategies, including a hybrid encoding, are implemented to address diverse scenarios. Leveraging Xilinx field-programmable gate array and Jetson Xavier NX, the proposed platform achieved remarkable performance gains. On the MNIST dataset, the platform demonstrated a 22.51x\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\times $$\end{document} speedup, 2.13% accuracy boost, and 14.79x\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\times $$\end{document} reduction in energy consumption. On the Fashion-MNIST dataset, it improved accuracy by 10.74% and the training speed by 1.89x\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargi

关键词： Spiking neural networks Encoding Spike-timing-dependent plasticity field-programmable gate array

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