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Design of an FPGA-based emulator for rapidly prototyping a nonvolatile system-on-a-chip

JAPANESE JOURNAL OF APPLIED PHYSICS 2025年第4期64卷 04SP06-04SP06页

作者： Suzuki, Daisuke Hanyu, Takahiro Univ Aizu 90 Kami IawaseTsurugaIkki Machi Aizu Wakamatsu Fukushima 9658580 Japan Tohoku Univ 2-1-1 KatahiraAoba Ku Sendai Miyagi 9808577 Japan

This paper presents a field-programmable gate array (FPGA)-based emulator for rapidly prototyping a non-volatile (NV)-FPGA-based system on chip (SoC) where an FPGA, a central processing unit, and other peripheral modules are integrated into a single chip to address the difficulty in estimating the usefulness of an NV-FPGA-based SoC on a target system. By mimicking the NV-memory device as a sequential logic circuit, a virtual NV-FPGA SoC is implemented on a commercial FPGA board, and its system-level functional verification is performed. As a typical design example, the proposed hardware is implemented on a Digilent Basys 3 board. A fundamental arithmetic logic circuit is implemented on the NV-FPGA, and its logical behavior is the same as that of the original circuit, and NV-logic-specific functions, i.e. store and recall operations are successfully confirmed. Additionally, a 96.3% power reduction is estimated by the NV-FPGA SoC compared to that of a volatile FPGA SoC system under 1.83% of activity ratio.

关键词： field-programmable gate array nonvolatile logic hardware emulation system on a chip prototyping

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Wearable sensor-based measurement and classification of athletic activities using FPGA and EdgeTPU

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PROCEEDINGS OF THE INSTITUTION OF MECHANICAL ENGINEERS PART P-JOURNAL OF SPORTS ENGINEERING AND TECHNOLOGY 2025年

作者： Muralikrishnan, P. Maheswari, M. K Ramakrishnan Coll Engn Samayapuram Kariyamanickam Rd Tiruchirappalli 621112 Tamil Nadu India

Wearable sensors, such as smartwatches, often face challenges in providing accurate readings due to variations in sensor quality and placement irregularities. Furthermore, deep convolutional neural networks (CNNs) can be resource-intensive, making them less suitable for real-time applications in wearable technology. This study introduces a novel approach utilizing Edge Tensor Processing Units (EdgeTPUs) combined with field-programmable gate arrays (FPGAs) for activity classification in athletes, specifically designed for resource-constrained environments. EdgeTPU models are optimized for low memory usage and high computational efficiency, making them ideal for microcontrollers used in wearable devices. To address model size and complexity, we employ quantization techniques and a lightweight neural network design. Experiments using the UCI-HAR, WISDM, and WEAR datasets show that our approach achieves a classification accuracy of 98.97%. The FPGA implementation offers high throughput and low latency, critical for real-time processing in wearable sensors. Additionally, we present three innovative approaches for complex loop optimization to enhance convolution efficiency. With a usage rate of 24.6%, the EdgeTPU model implemented on a Virtex-7 FPGA demonstrates effective hardware utilization. Our results indicate that the integration of FPGA and EdgeTPU technologies enables efficient real-time monitoring of athletic activities in wearable devices with limited resources.

关键词： Edge tensor processing unit athletic activities field-programmable gate array FPGA implementation signal classification

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FPGA-based performance evaluation of backstepping control and computed torque control for industrial robots

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INTERNATIONAL JOURNAL OF AUTOMATION AND CONTROL 2025年第1期19卷 101-132页

作者： Fekik, Arezki Khati, Hocine Azar, Ahmad Taher Hamida, Mohamed Lamine Denoun, Hakim Kamal, Nashwa Ahmad Univ Akli Mohand Oulhadj Bouria Dept Elect Engn Rue Drissi Yahia Bouira 10000 Algeria Nantes Univ Ecole Cent Nantes CNRS LS2NUMR 6004 F-44000 Nantes France Univ Mouloud Mammeri Tizi Ouzou Fac Elect & Comp Engn Dept Automat Design & Drive Prod Syst Lab Tizi Algeria Prince Sultan Univ Coll Comp & Informat Sci Riyadh 11586 Saudi Arabia Prince Sultan Univ Automated Syst & Soft Comp Lab ASSCL Riyadh Saudi Arabia Benha Univ Fac Comp & Artificial Intelligence Banha 13518 Egypt Elect Engn Adv Technol Lab LATAGE Tizi Algeria Cairo Univ Fac Engn Giza 12613 Egypt

In this paper, a comparative study is conducted on two nonlinear control techniques: state feedback control through backstepping and computed torque control. The study focuses on their application to the industrial robot PUMA 560. The primary goal is to assess the trajectory tracking accuracy and speed achieved by these methods. To achieve this objective, both control techniques are employed on the Zed board Zynq FPGA platform, encompassing both simulation and hardware systems. Subsequently, the experimental results are thoroughly analysed and compared, aiming to accentuate the unique advantages and constraints associated with each method.

关键词： field-programmable gate array FPGA backstepping control computed torque control CTC Zed board Zynq PUMA 560

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Using FPGA devices to accelerate the evaluation phase of tree-based genetic programming: an extended analysis

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GENETIC PROGRAMMING AND EVOLVABLE MACHINES 2025年第1期26卷 1-48页

作者： Crary, Christopher Piard, Wesley Stitt, Greg Hicks, Benjamin Bean, Caleb Burlacu, Bogdan Banzhaf, Wolfgang Univ Florida Dept Elect & Comp Engn Gainesville FL 32611 USA Univ Appl Sci Upper Austria Heurist & Evolutionary Algorithms Lab Hagenberg Upper Austria Austria Michigan State Univ Dept Comp Sci & Engn E Lansing MI USA

This paper establishes the potential of accelerating the evaluation phase of tree-based genetic programming through contemporary field-programmable gate array (FPGA) technology. This exploration stems from the fact that FPGAs can sometimes leverage increased levels of both data and function parallelism, as well as superior power/energy efficiency, when compared to general-purpose CPU/GPU systems. In this investigation, we introduce a fixed-depth, tree-based architecture that can fully parallelize tree evaluation for type-consistent primitives that are unrolled and pipelined. We show that our accelerator on a 14nm FPGA achieves an average speedup of 43x\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\times$$\end{document} when compared to a recent open-source GPU solution, TensorGP, implemented on 8nm process-node technology, and an average speedup of 4,902x\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\times$$\end{document} when compared to a popular baseline GP software tool, DEAP, running parallelized across all cores of a 2-socket, 28-core (56-thread), 14nm CPU server. Despite our single-FPGA accelerator being 2.4x\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\times$$\end{document} slower on average when compared to the recent state-of-the-art Operon tool executing on the same 2-processor, 28-core CPU system, we show that this single-FPGA system is 1.4x\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym}

关键词： Tree-based genetic programming field-programmable gate array Domain-specific architecture Hardware acceleration

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Educational CT Scanner Model Realization: A Case Study Using Laser Emitter and 3-D Printing

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IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT 2025年 74卷

作者： Prochazka, Michal Kasik, Vladimir Litschmannova, Martina Penhaker, Marek VSB Tech Univ Ostrava Fac Elect Engn & Comp Sci Dept Cybernet & Biomed Engn Ostrava 70800 Czech Republic VSB Tech Univ Ostrava Fac Elect Engn & Comp Sci Dept Appl Math Ostrava 70800 Czech Republic

Understanding the fundamental principles of computed tomography (CT) is essential for future healthcare professionals. To facilitate this learning process, we designed and constructed an educational model that closely resembles a third-generation medical CT scanner. This model enables users to grasp the mechanics of CT scanning, including the movement of the bed's height, bed translation, and gantry rotation. Utilizing a red linear laser, which does not require special safety measures, this model effectively demonstrates the CT scanning process by projecting visible red light beams and collecting projection data with phototransistors. The reconstruction of CT images is achieved using the inverse Radon transform, emphasizing simplicity and educational value over advanced medical CT techniques. Our evaluation of the model revealed that the pixel area was 2.67 mm(2), with bed translation dictating resolution along the bed axis. We observed distortions in the representation of sharp-edged objects during image reconstruction, illustrating potential measurement limits. Based on these findings, two phantoms were created, one of which was reconstructed in 3-D for comparison. This educational CT model provides a valuable tool that bridges the gap between theoretical knowledge and practical application, making the complex field of CT scanning more accessible and comprehensible for students and the public. This model not only enhances the understanding of CT principles but also provides a platform for further exploration and refinement in the field.

关键词： Computed tomography Computational modeling X-ray imaging Image reconstruction Data models Biomedical imaging Biological system modeling X-ray lasers Three-dimensional printing Data acquisition Biomedical engineering education computed tomography (CT) diode lasers field-programmable gate array

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Multiscroll hopfield neural network with extreme multistability and its application in video encryption for IIoT

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NEURAL NETWORKS 2025年 182卷 106904页

作者： Yu, Fei Lin, Yue Yao, Wei Cai, Shuo Lin, Hairong Li, Yi Changsha Univ Sci & Technol Sch Comp & Commun Engn Changsha 410114 Peoples R China Cent South Univ Sch Elect Informat Changsha 410083 Peoples R China Hunan Post & Telecommun Planning & Designing Inst Changsha 410126 Peoples R China

In Industrial Internet of Things (IIoT) production and operation processes, a substantial amount of video data is generated, often containing sensitive personal and commercial information. This paper proposed three new multiscroll Hopfield neural network (MHNN) systems by utilizing an improved segmented nonlinear non- ideal magnetic-controlled memristor model for electromagnetic radiation. Through dynamical methods, the constructed neural network's multidimensional multiscroll attractors and initial offset boosting behavior are analyzed. The observed initial offset boosting behavior demonstrates the system has extreme multistability. Secondly, a video encryption application based on the MHNN system is implemented on the Raspberry Pi platform. This approach encrypts each frame of the extracted video image using a novel encryption algorithm through frame-by-frame encryption, achieving significant encryption results with an information entropy calculation result of 7.9973. This provides strong protection for video data generated in IIoT. Finally, the proposed MHNN system is implemented on field-programmable gate array (FPGA) digital hardware platform.

关键词： Industrial internet of things Video encryption Multiscroll hopfield neural network Extreme multistability field-programmable gate array

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Optimized FFT Designs for High-Performance LTE and 5G Networks

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ARABIAN JOURNAL FOR SCIENCE AND ENGINEERING 2025年 1-20页

作者： Khan, Daud Jan, Latif Zafar, Mohammad Haseeb IQRA Natl Univ Dept Comp Sci Peshawar 25100 Khyber Pakhtunk Pakistan Cardiff Metropolitan Univ Cardiff Sch Technol Cardiff CF5 Wales

This paper proposes a run-time reconfigurable butterfly structure capable of simultaneously performing Radix-8, Radix-4, Radix-3, and Radix-2 Fast Fourier Transform (FFT) computations to cater to the bandwidth requirements of current Long-Term Evolution (LTE), Fifth Generation (5G), and beyond systems. While LTE and 5G promise exceptionally high throughput, ranging from 300 Mbps to 3 Gbps, field-programmable gate array (FPGA) and Application Specific Integrated Circuit vendors face significant challenges in meeting these demands. Efficient implementation strategies are essential for realizing these standards in silicon. Given that FFT is the cornerstone of 5G systems, its computational complexity poses challenges in meeting high throughput requirements. Furthermore, the flexibility to adapt to different bandwidths is crucial in 5G networks. Therefore, a configurable FFT engine that optimizes resource utilization while providing high throughput is highly desirable. This paper presents two FFT architectures based on the proposed reconfigurable butterfly, offering designers the flexibility to choose the most suitable approach for realizing efficient and high-throughput solutions tailored to the requirements of 5G and beyond.

关键词： Fast Fourier transform field-programmable gate array Application specific integrated circuit 5th generation Long-term evolution

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Efficient Co-Approximate Parallel Compressive Depth Reconstruction on FPGA

Efficient Co-Approximate Parallel Compressive Depth Reconstr...

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2025 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2025

作者： Wu, Yun McAllister, John School of Electrical Electronic and Computer Engineering Queen's University Belfast United Kingdom

ISBN: (纸本)9798350368741

Efficient depth image reconstruction from sparse samples is crucial for machine perception applications, such as robotics, vehicle assistance and autonomy. It demands fast processing speed with low power consumption for sensing quality and safety, as well as cost reduction for FPGA and solid state implementations, within constrained resource budgets on edge devices. A new co-approximate framework of parallel approximate compressive depth reconstruction engine on FPGA is proposed using 1 solvers, proximal gradient decent (PGD), with instrumented frequency and voltage scaling during the iterative optimization process. By evaluating various number of parallel approximate processing units for the depth image reconstruction engine, up to 51% further power saving is achieved, and 421× speed up of parallel processing compared to the baseline, henceforth the efficiency is elevated over 43×. © 2025 IEEE.

关键词： Approximate Computing Compressive Sensing Convex Optimization Depth Reconstruction field-programmable gate array

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Design and analysis of a dual mode CMOS field programmable analog array

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Journal of Semiconductors 2014年第10期35卷 152-162页

作者：程小燕杨海钢尹韬吴其松张洪锋刘飞 Institute of Electronics Chinese Academy of Sciences University of Chinese Academy of Sciences

This paper presents a novel field-programmable analog array （FPAA） architecture featuring a dual mode including discrete-time （DT） and continuous-time （CT） operation modes, along with a highly routable connection boxes （CBs） based interconnection lattice. The dual mode circuit for the FPAA is capable of achieving targeted op- timal performance in different applications. The architecture utilizes routing switches in a CB not only for the signal interconnection purpose but also for control of the electrical charge transfer required in switched-capacitor circuits. This way, the performance of the circuit in either mode shall not be hampered with adding of programmability. The proposed FPAA is designed and implemented in a 0.18 μm standard CMOS process with a 3.3 V supply voltage. The result from post-layout simulation shows that a maximum bandwidth of 265 MHz through the interconnection network is achieved. The measured results from demonstrated examples show that the maximum signal bandwidth of up to 2 MHz in CT mode is obtained with the spurious free dynamic range of 54 dB, while the signal processing precision in DT mode reaches 96.4%.

关键词： field-programmable gate array field-programmable analog array configurable analog block rail-to- rail biquadratic filters

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Design methodology of digital sensors for detecting laser fault injection attacks in FPGAs

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Journal of Cryptographic Engineering 2025年第2期15卷 1-16页

作者： Hayashi, Shungo Sakamoto, Junichi Matsumoto, Tsutomu Cyber Physical Security Research Institute National Institute of Advanced Industrial Science and Technology 2-3-26 Aomi Tokyo Koto-ku 135-0064 Japan Environment and Information Science Yokohama National University Tokiwadai 79-7 Kanagawa Hodogayaku Yokohama 240-8501 Japan

Laser fault injection (LFI) refers to a serious attack that modifies programs and data in embedded systems by introducing specific errors into a device in operation. As a countermeasure, in addition to duplication and optical sensors, the detection of LFIs using a sensor composed of digital circuits has recently been proposed. However, the research on the physical layout of these sensors is limited. In this work, we profile the laser irradiation position and its effect on the surrounding circuits by laser-scanning experiments on field-programmable gate arrays (FPGAs). Studies have shown that digital sensors with conventional designs have low-sensitivity areas with regard to LFIs. To improve LFI detection in FPGAs, we propose a design method for digital sensors and apply it to a ring oscillator (RO)-based digital sensor and a time-to-digital converter-based sensor. Experimental results show that the RO-based sensor based on the proposed method increased the area detecting LFI to about twice that of the conventional method, and detect 99.8% of the effective faults at the target register under protection. Furthermore, we extend the application of the RO-based sensor based on the proposed method to the protection of cryptographic circuits. The results of the laser-scanning experiment show that the proposed sensor detected 98.3% of the LFIs that caused effective faults in the cryptographic circuit. © The Author(s) 2025.

关键词： Digital sensor Fault injection attack field-programmable gate array Laser fault injection Ring oscillator Time-to-digital converter

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