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ReLiCADA: Reservoir Computing Using Linear Cellular Automata design algorithm

COMPLEX & INTELLIGENT SYSTEMS 2024年第3期10卷 3593-3616页

作者： Kantic, Jonas Legl, Fabian C. Stechele, Walter Hermann, Jakob TUM Sch Computat Informat & Technol Dept Comp Engn Arcisstr 21 D-80333 Munich Germany IfTA Ingenieurburo Thermoakust GmbH Junkersstr 8 D-82178 Puchheim Germany

In this paper, we present a novel algorithm to optimize the design of Reservoir Computing using Cellular Automata models for time series applications. Besides selecting the models' hyperparameters, the proposed algorithm particularly solves the open problem of Linear Cellular Automaton rule selection. The selection method pre-selects only a few promising candidate rules out of an exponentially growing rule space. When applied to relevant benchmark datasets, the selected rules achieve low errors, with the best rules being among the top 5% of the overall rule space. The algorithm was developed based on mathematical analysis of Linear Cellular Automaton properties and is backed by almost one million experiments, adding up to a computational runtime of nearly one year. Comparisons to other state-of-the-art time series models show that the proposed Reservoir Computing using Cellular Automata models have lower computational complexity and, at the same time, achieve lower errors. Hence, our approach reduces the time needed for training and hyperparameter optimization by up to several orders of magnitude.

关键词： Cellular Automata Dynamical system Edge of Chaos field-programmable gate array Reservoir Computing Time series prediction

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Design methodology of digital sensors for detecting laser fault injection attacks in FPGAs

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JOURNAL OF CRYPTOGRAPHIC ENGINEERING 2025年第2期15卷 1-16页

作者： Hayashi, Shungo Sakamoto, Junichi Matsumoto, Tsutomu Natl Inst Adv Ind Sci & Technol Cyber Phys Secur Res Inst 2-3-26 AomiKoto Ku Tokyo 1350064 Japan Yokohama Natl Univ Environm & Informat Sci Tokiwadai 79-7 Yokohama Kanagawa 2408501 Japan

Laser fault injection (LFI) refers to a serious attack that modifies programs and data in embedded systems by introducing specific errors into a device in operation. As a countermeasure, in addition to duplication and optical sensors, the detection of LFIs using a sensor composed of digital circuits has recently been proposed. However, the research on the physical layout of these sensors is limited. In this work, we profile the laser irradiation position and its effect on the surrounding circuits by laser-scanning experiments on field-programmable gate arrays (FPGAs). Studies have shown that digital sensors with conventional designs have low-sensitivity areas with regard to LFIs. To improve LFI detection in FPGAs, we propose a design method for digital sensors and apply it to a ring oscillator (RO)-based digital sensor and a time-to-digital converter-based sensor. Experimental results show that the RO-based sensor based on the proposed method increased the area detecting LFI to about twice that of the conventional method, and detect 99.8% of the effective faults at the target register under protection. Furthermore, we extend the application of the RO-based sensor based on the proposed method to the protection of cryptographic circuits. The results of the laser-scanning experiment show that the proposed sensor detected 98.3% of the LFIs that caused effective faults in the cryptographic circuit.

关键词： Fault injection attack Laser fault injection Ring oscillator Time-to-digital converter field-programmable gate array Digital sensor

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High-efficiency TRNG Design Based on Multi-bit Dual-ring Oscillator

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ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS 2023年第4期16卷 1-23页

作者： Yingchun Lu Yun Yang Rong Hu Huaguo Liang Maoxiang Yi Huang Zhengfeng Yuanming Ma Tian Chen Liang Yao Hefei Univ Technol Sch Microelect 193 Tunxi Rd Hefei 230601 Anhui Peoples R China Hefei Univ Technol Sch Comp & Informat Technol 193 Tunxi Rd Hefei 230601 Anhui Peoples R China Anhui Univ Sch Integrated Circuits 111 Jiulong Rd Hefei 230039 Anhui Peoples R China

Unpredictable true random numbers are required in security technology fields such as information encryption, key generation, mask generation for anti-side-channel analysis, algorithm initialization, and so on. At present, the true random number generator (TRNG) is not enough to provide fast random bits by low-speed bits generation. Therefore, it is necessary to design a faster TRNG. This work presents an ultra-compact TRNG with high throughput based on a novel extendable dual-ring oscillator (DRO). Owing to multiple bits output per cycle in DRO can be used to obtain the original random sequence, the proposed DRO achieves a maximum resource utilization to build a more efficient TRNG, compared with the conventional TRNG system based on ring oscillator (RO), which only has a single output and needs to build multiple groups of ring oscillators. TRNG based on the 2-bit DRO and its 8-bit derivative structure has been verified on Xilinx Artix-7 and Kintex-7 FPGA under the automatic layout and routing and has achieved a throughput of 550 Mbps and 1,100 Mbps, respectively. Moreover, in terms of throughput performance over operating frequency, hardware consumption, and entropy, the proposed scheme has obvious advantages. Finally, the generated sequences show good randomness in the test of NIST SP800-22 and Dieharder test suite and pass the entropy estimation test kit NIST SP800-90B and AIS-31.

关键词： True random number generator field-programmable gate array Dual-ring oscillator

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Constraint-Aware Multi-Technique Approximate High-Level Synthesis for FPGAs

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ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS 2023年第4期16卷 1-28页

作者： Leipnitz, Marcos T. Nazar, Gabriel L. Inst Informat Fed Univ Rio Grande Do Sul 9500 Bento Gonc Alves Ave BR-91501970 Porto Alegre RS Brazil

Numerous approximate computing (AC) techniques have been developed to reduce the design costs in error-resilient application domains, such as signal and multimedia processing, data mining, machine learning, and computer vision, to trade-off computation accuracy with area and power savings or performance improvements. Selecting adequate techniques for each application and optimization target is complex but crucial for high-quality results. In this context, Approximate High-Level Synthesis (AHLS) tools have been proposed to alleviate the burden of hand-crafting approximate circuits by automating the exploitation of AC techniques. However, such tools are typically tied to a specific approximation technique or a difficult-to-extend set of techniques whose exploitation is not fully automated or steered by optimization targets. Therefore, available AHLS tools overlook the benefits of expanding the design space by mixing diverse approximation techniques toward meeting specific design objectives with minimum error. In this work, we propose an AHLS design methodology for FPGAs that automatically identifies efficient combinations of multiple approximation techniques for different applications and design constraints. Compared to single-technique approaches, decreases of up to 30% in mean squared error and absolute increases of up to 6.5% in percentage accuracy were obtained for a set of image, video, signal processing and machine learning benchmarks.

关键词： High-level synthesis approximate computing field-programmable gate array design space exploration

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Low-Complexity Square-Root Unscented Kalman Filter Design Methodology

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CIRCUITS SYSTEMS AND SIGNAL PROCESSING 2023年第11期42卷 6900-6928页

作者： Dutt, Rashi Acharyya, Amit Indian Inst Technol Hyderabad Dept Elect Engn Hyderabad 502285 Telangana India

Square-root unscented Kalman filter (SRUKF) is a widely used state estimator for several state of-the-art, highly nonlinear, and critical applications. It improves the stability and numerical accuracy of the system compared to the non-square root formulation, the unscented Kalman filter (UKF). At the same time, SRUKF is less computationally intensive compared to UKF, making it suitable for portable and battery-powered applications. This paper proposes a low-complexity and power-efficient architecture design methodology for SRUKF presented with a use case of the simultaneous localization and mapping (SLAM) problem. Implementation results show that the proposed SRUKF methodology is highly stable and achieves higher accuracy than the extensively used extended Kalman filter and UKF when developed for highly critical nonlinear applications such as SLAM. The design is synthesized and implemented on resource constraint Zynq-7000 XC7Z020 FPGA-based Zedboard development kit and compared with the state-of-the-art Kalman filter-based FPGA designs. Synthesis results show that the architecture is highly stable and has significant computation savings in DSP cores and clock cycles. The power consumption was reduced by 64% compared to the state-ofthe-art UKF design methodology. ASIC design was synthesized using UMC 90-nm technology, and the results for on-chip area and power consumption results have been discussed.

关键词： Square-root unscented Kalman filter Low-complexity VLSI architecture Householder coordinate rotation digital computer (CORDIC) field-programmable gate array ASIC SLAM

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Profile generation using the filtering technique for the fast motion and smooth performance in the hardware level of autonomous system

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IET SCIENCE MEASUREMENT & TECHNOLOGY 2023年第8期17卷 330-350页

作者： Lam, Duc Khai Ngo, Nhat Minh Ngo, Ha Quang Thinh Univ Informat Technol Comp Engn Dept Ho Chi Minh City Vietnam Ho Chi Minh City Univ Technol HCMUT Fac Mech Engn Dept Mechatron Ho Chi Minh City Vietnam Vietnam Natl Univ Ho Chi Minh City VNU HCM Ho Chi Minh City Vietnam Ho Chi Minh City Univ Technol HCMUT 268 Ly Thuong KietDist 10 Ho Chi Minh Vietnam

This study addresses the challenge of motion control in autonomousvehicles through the introduction of a novel profile generation design. Specifically,autonomous vehicles often contend with uncertain factors and physicallimitations within their operational environments, such as abrupt changes inacceleration or intricate parametric motion profiles. To tackle this problem, afiltering technique for motion profile generation is proposed, leveraging ahardware programming language as its foundation. The investigation begins byanalyzing the specific structure of the mobile platform, which includes twoactive side wheels, two passive rear wheels, a high load capacity, and adifferential drive mode. Building upon this theoretical basis, the proposedfiltering technique is introduced to attain smooth motion profiles and optimizetiming. Furthermore, the study suggests the use of FPGA (field programmablegate array) acceleration to expedite these computations for swift motionprocessing. To validate the efficacy of the proposed method, both the mobilevehicle and the load are simulated as a one-axis linear ball-screw system withan aluminum ruler. The experimental results unequivocally demonstrate theeffectiveness, feasibility, and applicability of the proposed approach across avariety of industrial solutions. The filtering technique to generatemotion profile based on the hardware programming language is introduced. First,the specific structure of mobile platform involves two active side wheels andtwo passive rear wheels. Second, theoretical control using the polynomialfunction is mentioned to provide the concrete basis. Third, field programmablegate array-accelerated approach is additionally implemented thesecomputations for rapid ***

关键词： autonomous vehicle digital signal processing field-programmable gate array filtering technique motion planning

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Digital Filter Architecture Based on Modified Winograd Method F(2x 2, 5x 5) and Residue Number System

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IEEE ACCESS 2023年 11卷 26807-26819页

作者： Valuev, Georgii Valueva, Maria Babenko, Mikhail Tchernykh, Andrei North Caucasus Fed Univ North Caucasus Ctr Math Res Stavropol 355017 Russia Ivannikov Inst Syst Programming Control Management & Appl Math Moscow 109004 Russia CICESE Res Ctr Comp Sci Dept Ensenada 22800 Mexico

Improving the characteristics of digital signal processing devices is an important task in many practical problems. The paper proposes the architecture of a two-dimensional digital filter with a $5\times 5$ mask, in which calculations are performed according to the Winograd method in the Residue Number System (RNS) with moduli of a special type. Theoretical analysis and hardware field-programmable gate array simulation are presented. The results show that the fragment throughput fr/s (number of fragments per second) of the device is 29.6%- 724.7% higher than state-of-the-art solutions. This is achieved by the combination of the Winograd method, which reduces the number of multiplications, with the RNS arithmetic, which performs addition and multiplication under smaller operands in parallel. However, our experiments showed that the proposed method requires up to 2.54%- 11.01% more Look-Up Tables and 3.58%- 19.83% higher power consumption compared to known analogues.

关键词： Filtering Finite impulse response filters Performance evaluation IIR filters Hardware Filtering algorithms Computer architecture Residue number system winograd method field-programmable gate array digital filter digital signal processing

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Dynamic measurement with in-cycle process excitation of HCCI combustion: The key to handle complexity of data-driven control?

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INTERNATIONAL JOURNAL OF ENGINE RESEARCH 2023年第3期24卷 1155-1174页

作者： Bedei, Julian Oberlies, Malte Schaber, Patrick Gordon, David Nuss, Eugen Li, Liguang Andert, Jakob Rhein Westfal TH Aachen Teaching & Res Area Mechatron Mobile Prop Aachen Germany Univ Alberta Dept Mech Engn Edmonton AB Canada Rhein Westfal TH Aachen Inst Automat Control Aachen Germany Tongji Univ Sch Automot Studies Shanghai Peoples R China

Homogeneous Charge Compression Ignition (HCCI) is a low temperature combustion technique with a high potential for reducing emissions while simultaneously improving fuel consumption. However, the high sensitivity to changing boundary conditions and low combustion stability at the edges of the operating range has lead to implementation challenges. Additionally, cyclic coupling through internal exhaust gas recirculation causes cyclic variations of the process, resulting in incomplete combustion, or even misfiring. Thus, consecutive cycles must be decoupled to increase the process stability. To achieve an accurate description of the coupling effects on a cycle-to-cycle and an inner-cyclic timescale, a novel measurement methodology is presented to generate data with a high variance. For this purpose, an active process excitation is performed to capture all relevant interactions between operating and feedback variables to enable modeling of the coupling effects on both timescales. To demonstrate the potential of the methodology, the generated data is used to design multiple input, multiple output (MIMO) models for both cyclic and inner-cyclic timescales. Artificial neural networks are then utilized to address the highly nonlinear process by taking advantage of the large amount of training data. Inverse process models are then used to implement a pure cycle-to-cycle and a multiscale MIMO closed-loop controller. Compared to state-of-the-art rule-based control approaches, the process stability and its thermodynamic efficiency are significantly improved. For the multiscale MIMO controller, a reduction of the standard deviation of the indicated mean effective pressure and the combustion phasing of more than 65% is achieved. In particular, the additional inner-cyclic feedback loop achieves a remarkable reduction of the standard deviation of approximately 35% and a 1.2% higher indicated efficiency compared to the cycle-to-cycle MIMO controller. The dynamic measurement with acti

关键词： Homogeneous charge compression ignition field-programmable gate array cylinder-pressure-indication control artificial neural network nonlinear model predictive control multiple input multiple output

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FPGA implementation of AES encryptor based on rolled and masked approach

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INTERNATIONAL JOURNAL OF INFORMATION AND COMPUTER SECURITY 2023年第1-2期21卷 1-18页

作者： Mathur, Monika Goel, Nidhi IGDTUW Dept ECE Kashmere Gate Delhi India

The present work proposes a modified 8-bit AES architecture that performs AES core operations in a single round wherein data is iterated ten times instead of having ten different rounds leading to substantial decrease in area and power consumption. To enhance the security of AES encryption, boolean masking has been employed for all AES operations, rounds and intermediate data. Modified architecture for AddRoundKey and ByteSubstitution operation has been proposed that employs high order masking. Also, an enhanced key expansion algorithm is proposed that makes AES less vulnerable to saturation attacks and differential power analysis (DPA) attacks. Implementation of the proposed architecture has been done using Vivado Design Suite on Virtex-7 FPGA. Result analysis depicts that, during the performance explore strategy, 179.73 MHz maximum frequency with a throughput of 143.78 Mbps has been achieved whereas, the proposed architecture utilises 757 slices, 962 LUTs and 0.313 watt power using area explore strategy.

关键词： advanced encryption standard AES field-programmable gate array FPGA Boolean masking enhanced key expansion algorithm DPA attack rolled architecture

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FPGA-based Low-Latency Audio Coprocessor for Networked Music Performance 4

FPGA-based Low-Latency Audio Coprocessor for Networked Music...

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4th International Symposium on the Internet of Sounds (IOS RN)

作者： Bert, Diego Domini, Nicola Peloso, Riccardo Severi, Leonardo Sacchetto, Matteo Bianco, Andrea Rottondi, Cristina Politecn Torino Dept Elect & Telecommun Turin Italy

ISBN: (纸本)9798350382549

Networked Music Performance (NMP) applications are acknowledged to be a particularly challenging field due to their stringent latency requirements and their demand for high audio quality. Most solutions developed in the last decades tried to overcome these obstacles by leveraging software approaches, that can introduce excessive time delays as a consequence of the general-purpose nature of the architectures on which they are implemented. Alternatively, a dedicated audio processor can be employed to minimize the mouth-to-ear latency. This paper presents the ongoing development of an hardware system that exploits an Application-Specific Instruction set Processor (ASIP) implemented on a field-programmable gate array (FPGA) to accelerate audio sample management. Specifically, a Transport Triggered Architecture (TTA) is being investigated as a processor design that aligns well with the required application domains. Preliminary empirical results indicate that the proposed solution has the potential to achieve extremely low latency, compatible with NMP requirements. Further optimizations and enhancements are actively being pursued to address the yet open challenges posed by NMP applications.

关键词： Networked Music Performance audio latency audio processing field-programmable gate array

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