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International Journal of Systematic Innovation 2025年第1期9卷 78-97页

作者： Pravalika, Nazarkar Jabeena, A. Rajamani, Vetriveeran School of Electronics Engineering Vellore Institute of Technology Tamil Nadu Vellore India

Atherosclerotic disorders, such as peripheral artery disease (PAD), have a significant negative impact on patient outcomes. Inadequate treatment and poor detection rates can result in cardiovascular complications and limb loss. There is great promise for improving the detection and treatment of PAD and other medical disorders through machine learning (ML) and artificial intelligence (AI) techniques. This paper highlights the use of field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs) to implement the fundamental ideas of AI and ML, specifically in the treatment of PAD. It emphasizes how these technologies can enhance drug selection, improve patient care, and refine disease phenotyping. This paper also describes how the integration of AI and ML with FPGA and ASIC technology can provide accurate and effective solutions to complex medical challenges, representing a significant breakthrough in medical analytics. © (2025), (Society of Sytematic Innovation). All rights reserved.

关键词： Application-Specific Integrated Circuits field-programmable gate arrays Machine Learning Peripheral Arterial Disease

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SC Build: a computer-aided design tool for design space exploration of embedded central processing unit cores for field-programmable gate arrays

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IET COMPUTERS AND DIGITAL TECHNIQUES 2009年第1期3卷 24-32页

作者： Anderson, I. D. L. Khalid, M. A. S. Univ Windsor RCIM Dept Elect & Comp Engn Windsor ON N9B 3P4 Canada

A genetic algorithm-based design space exploration technique using parameterised cores is examined. A computer-aided design tool called SCBuild was developed which is capable of applying a genetic algorithm to a core's parameters, and generating hardware description language models of core variants. The tool can also compute estimates of a variant's area and critical path delay on a field-programmable gate array. Using this tool, several experiments were conducted using a soft-core processor with a large design space. It was concluded from these experiments that using a genetic algorithm to explore the design space of a parameterised core can help a designer make intelligent decisions regarding the assignment of values to the parameters of an embedded hardware platform.

关键词： hardware description language computer-aided design tool embedded central processing unit cores SC Build field-programmable gate arrays parameterised cores logic CAD hardware description languages microprocessor chips design space exploration soft-core processor genetic algorithm field programmable gate arrays genetic algorithms

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THE CASE FOR EMBEDDED NETWORKS ON CHIP ON field-programmable gate arrays

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IEEE MICRO 2014年第1期34卷 80-89页

作者： Abdelfattah, Mohamed S. Betz, Vaughn Univ Toronto Dept Elect & Comp Engn Toronto ON M5S 3G4 Canada

THE AUTHORS PROPOSE AUGMENTING THE FPGA ARCHITECTURE WITH AN EMBEDDED NETWORK ON CHIP TO IMPLEMENT THE SYSTEM-LEVEL COMMUNICATION INFRASTRUCTURE AND MITIgate THE HARDWARE DESIGN CHALLENGES FACED BY CURRENT BUS-BASED INTERCONNECTS. WITH A FLEXIBLE INTERFACE BETWEEN THE NOC AND THE FPGA FABRIC, AN EMBEDDED NOC MAINTAINS CONFIGURABILITY AND SIMPLIFIES THE DISTRIBUTION OF I/O DATA THROUGHOUT THE CHIP, AND IS ALWAYS MORE ENERGY-EFFICIENT COMPARED TO CUSTOM BUSES CONFIGURED INTO THE FABRIC.

关键词： Embedded systems field programmable gate arrays field-programmable gate arrays FPGA I/O and data communications interconnections Kernel Network-on-chip networks-on-chip Reconfigurable architectures System-on-chip

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Dataflow computation with intelligent memories emulated on field-programmable gate arrays (FPGAs)

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MICROPROCESSORS AND MICROSYSTEMS 2002年第6期26卷 263-280页

作者： Ingersoll, S Ziavras, SG New Jersey Inst Technol Dept Elect & Comp Engn Newark NJ 07102 USA

This paper presents a new design that implements the data-driven (i.e. dataflow) computation paradigm with intelligent memories. Also, a relevant prototype that employs FPGAs is presented for the support of intelligent memory structures. Instead of giving the CPU the privileged right to decide what instructions to fetch in each cycle (as is the case for control-flow CPUs), instructions in dataflow computers enter the execution unit on their own when they are ready to execute. This way, the application-knowledgeable algorithm, rather than the application-ignorant CPU, is in control. This approach could eventually result in outstanding performance and elimination of large numbers of redundant operations that plague current control-flow designs. Control-flow and dataflow machines are two extreme computation paradigms. In their pure form, the former machines follow an inherently sequential execution process while the latter are parallel in nature. The sequential nature of control-flow machines makes them relatively easy to implement compared to dataflow machines, which have to address a number of issues that are easily solved in the realm of the control-flow paradigm. Our dataflow design solves these issues at the intelligent memory level, separating the processor from dataflow maintenance tasks. It is shown that using intelligent memories with basic components similar to those of FPGAs produces a feasible approach. Expected improvements within the next few years in underlying intelligent memory and FPGA technologies will have the potential to make the effect of our approach even more dramatic. (C) 2002 Elsevier Science B.V. All rights reserved.

关键词： dataflow computation field-programmable gate arrays prototyping intelligent memories

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ARCHITECTURE OF field-programmable gate arrays

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PROCEEDINGS OF THE IEEE 1993年第7期81卷 1013-1029页

作者： ROSE, J ELGAMAL, A SANGIOVANNIVINCENTELLI, A STANFORD UNIV DEPT ELECT ENGNSTANFORDCA 94305 UNIV CALIF BERKELEY DEPT ELECT ENGN & COMP SCIBERKELEYCA 94720

A survey of field-programmable gate Array (FPGA) architectures and the programming technologies used to customize them is presented. Programming technologies are compared on the basis of their volatility, size, parasitic capacitance, resistance, and process technology complexity. FPGA architectures are divided into two constituents: logic block architectures and routing architectures. A classification of logic blocks based on their granularity is proposed and several logic blocks used in commercially available FPGA's are described. A brief review of recent results on the effect of logic block granularity on logic density and performance of an FPGA is then presented. Several commercial routing architectures are described in the context of a general routing architecture modeL Finally, recent results on the tradeoff between the flexibility of an FPGA routing architecture its routability and density are reviewed.

关键词： FPGA architectures PLD programming application specific integrated circuits field-programmable gate arrays granularity logic arrays logic block architectures logic density network routing parasitic capacitance process technology complexity programming technologies resistance routing architectures

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Segmented routing for speed-performance and routability in field-programmable gate arrays

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VLSI DESIGN 1996年第4期4卷 275-291页

作者： Brown, S Khellah, M Lemieux, G Department of Electrical and Computer Engineering University of Toronto Canada

This paper addresses several issues involved for routing in field-programmable gate arrays (FPGAs) that have both horizontal and vertical routing channels, with wire segments of various lengths. Routing is studied by using CAD routing tools to map a set of benchmark circuits into FPGAs, and measuring the effects that various parameters of the CAD tools have on the implementation of the circuits. A two-stage routing strategy of global followed by detailed routing is used, and the effects of both of these CAD stages are discussed, with emphasis on detailed routing, We present a new detailed routing algorithm designed specifically for the types of routing structures found in the most recent generation of FPGAs, and show that the new algorithm achieves significantly better results than previously published FPGA routers with respect to the speed-performance of implemented circuits. The experiments presented in this paper address both of the key metrics for FPGA routing tools, namely the effective utilization of available interconnect resources in an FPGA, and the speed-performance of implemented circuits. The major contributions of this research include the following: 1) we illustrate the effect of a global router on both area-utilization and speed-performance of implemented circuits, 2) experiments quantify the impact of the detailed router cost functions on area-utilization and speed-performance, 3) we show the effect on circuit implementation of dividing multi-point nets in a circuit being routed into point-to-point connections, and 4) the paper illustrates that CAD routing tools should account for both routability and speed-performance at the same time, not just focus on one goal.

关键词： field-programmable gate arrays FPGAs CAD routability speed-performance

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CRITICAL PATH-ANALYSIS FOR field-programmable gate arrays

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MICROPROCESSORS AND MICROSYSTEMS 1995年第7期19卷 435-439页

作者： [Anonymous] Texas Instruments

Device speed, or timing, is a critical aspect of system design. A realistic estimate of the achievable system speed is often required early in the design phase to avoid waste of valuable design time. System speed, of course, depends on the operation of all system components. This application note describes how to estimate the timing constraints of a field-programmable gate array (FPGA) design. However, the FPGA is only one component within the design: other devices also affect the system speed.

关键词： CRITICAL PATH ANALYSIS field-programmable gate arrays TIMING CONSTRAINTS

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General technology mapping for field-programmable gate arrays based on lookup tables

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ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS 2002年第1期7卷 1-32页

作者： Chowdhary, A Hayes, JP Intel Corp Santa Clara CA 95052 USA Univ Michigan Dept Elect Engn & Comp Sci Ann Arbor MI 48109 USA

We present a general technology-mapping methodology (TULIP) for field-programmable gate arrays (FPGAs) that can yield optimal results, and is applicable to any FPGA with a logic block composed of lookup tables (LUTs). We introduce the concept of a virtual switch to model the internal connections of a logic block with multiple LUTs;each configuration of virtual switches is called a multiple-LUT block (MLB). A logic block can be precisely defined by a small but complete set of representative configurations called an MLB basis. The MLB bases for various commercial FPGA families are demonstrated. Given a logic block represented by its MLB basis, technology mapping is precisely formulated as a graph-covering problem, which is transformed into a mixed integer-linear programming (MILP) optimization problem in order to achieve our optimality and generality objectives. The MILP model is solved using a general-purpose MILP solver tool. The results of using TULIP for mapping some ISCAS-85 benchmark circuits to a variety of logic blocks are presented. Circuits of a few hundred gates can be mapped directly in a few minutes. To map larger circuits to complex logic blocks, some approximation techniques are proposed based on partitioning the input circuit and simplifying the MLB basis. We show that these approximations result in close-to-optimal mappings of the benchmark circuits.

关键词： design theory basis circuit partitioning field-programmable gate arrays lookup tables (LUTs) mapping multiple-LUT blocks nonrooted trees rooted trees synthesis

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A scalable architecture for Variable Block Size Motion Estimation on field-programmable gate arrays

A scalable architecture for Variable Block Size Motion Estim...

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Canadian Conference on Electrical and Computer Engineering

作者： Moorthy, Theepan Ye, Andy Ryerson Univ Dept Elect & Comp Engn Toronto ON M5B 2K3 Canada

ISBN: (纸本)9781424416424

The flexibility of field-programmable gate arrays (FPGAs) encourages design reuse and can greatly enhance the upgradability of digital systems. This flexibility is particularly useful in the design of highly flexible video encoding systems that can accommodate a multitude of existing standards as well as the rapid emergence of new standards. In this paper, we investigate the use of FPGAs in the design of a highly scalable Variable Block Size Motion Estimation (VBSME) architecture for the H.264/AVC video encoding standard. The scalability of the architecture allows one to incorporate the system into low cost single FPGA solutions for low resolution encoding applications as well as into high performance multi-FPGA solutions targeting high-resolution video encoding applications. To overcome the performance gap between FPGAs and Application Specific Integrated Circuits (ASICs), our algorithm intelligently increases its parallelism as the design scales while minimizing the use of memory bandwidth. The core computing unit of the architecture is implemented on FPGAs and its performance is reported in this paper. It is shown that the computing unit is able to achieve real-time 40 fps performance for 640x480 resolution VGA video while incurring only 4% device utilization on a Xilinx XC5VLX330 (Virtex-5) FPGA. With 8 computing units (at 36% device utilization), the architecture is able to achieve real-time 45 fps performance for encoding full 1920x1088 progressive HDTV video.

关键词： Variable Block Size Motion Estimation H.264/AVC field-programmable gate arrays

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Implementation of Massive Artificial Neural Networks with field-programmable gate arrays

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IFAC Proceedings Volumes 2012年第4期45卷 133-138页

作者： Verber Domen Bračič Simon University of Maribor Faculty of Electrical Engineering and Computer Science Maribor Slovenia

This paper presents a novel method for implementing massive artificial neural networks (ANN) with field-programmable gate arrays (FPGA). Because of the sequential nature of programs, the execution of large ANNs in software is inefficient. On the other hand, in FPGA devices that consist of a large number of programmable circuits, the nodes of ANN may be executed in parallel. This provides for higher computational rates and a greater degree of robustness or fault tolerance than in conventional computers. The main goal of these studies was to implement as many neurons as possible on a single FPGA device, without giving up the minimal execution times. In the proposed solution, each neuron is implemented by a single multiplier. For the nonlinear behaviour of a neuron, the activation function is approximated using several linear segments. In order to overcome the limited memory capacity of FPGA, external memory is employed Execution of ANN is controlled by an embedded soft processor.

关键词： Computational intelligence artificial neural networks field-programmable gate arrays parallel computation

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