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Design and Applications for Embedded Networks-on-Chip on FPGAs

IEEE TRANSACTIONS ON COMPUTERS 2017年第6期66卷 1008-1021页

作者： Abdelfattah, Mohamed S. Bitar, Andrew Betz, Vaughn Univ Toronto Dept Elect & Comp Engn Toronto ON M5S Canada

field-programmable gate-arrays (FPGAs) have evolved to include embedded memory, high-speed I/O interfaces and processors, making them both more efficient and easier-to-use for compute acceleration and networking applications. However, implementing on-chip communication is still a designer's burden wherein custom system-level buses are implemented using the fine-grained FPGA logic and interconnect fabric. Instead, we propose augmenting FPGAs with an embedded network-on-chip (NoC) to implement system-level communication. We design custom interfaces to connect a packet-switched NoC to the FPGA fabric and I/Os in a configurable and efficient way and then define the necessary conditions to implement common FPGA design styles with an embedded NoC. Four application case studies highlight the advantages of using an embedded NoC. We show that access latency to external memory can be similar to 1.5 x lower. Our application case study with image compression shows that an embedded NoC improves frequency by 10-80%, reduces utilization of scarce long wires by 40% and makes design easier and more predictable. Additionally, we leverage the embedded NoC in creating a programmable Ethernet switch that can support up to 819 Gb/s-5 x more switching bandwidth and 3x lower area compared to previous work. Finally, we design a 400 Gb/s NoC-based packet processor that is very flexible and more efficient than other FPGA-based packet processors.

关键词： field-programmable gate-array network-on-chip latency-insensitive image compression networking packet processing

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ISO/OSI compliant network-on-chip implementation for CNN applications

ISO/OSI compliant network-on-chip implementation for CNN app...

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Conference on Bioengineered and Bioinspired Systems II

作者： Malki, S Hansson, A Spaanenburg, L Åkesson, B Lund Univ Dept Informat Technol S-22100 Lund Sweden

ISBN: (纸本)0819458341

The paper investigates the potential for a packet switching network for real-time image processing by a Cellular Neural Network (CNN) implemented on a field-programmable gate-array (FPGA). The implementation of a CNN requires several parameter restrictions with respect to the universal concept. For instance, the number representation and the cloning template are often confined to respectively 8 bits and a neighborhood of 1. It has been shown that optimal (i.e. minimal level) CNN architectures as derived from a morphological specification of the desired operation lead to arbitrarily large templates. A subsequent transformation step can turn this into a sequence of smaller templates for a specified hardware platform. The existence of a generic platform that can already handle the universal CNN architecture for prototyping and verification eliminates this need for technology-driven performance degradation. The proposed packet switcher consists of a physical layer where the CNN nodal function is performed, a data-link layer where the nodal data are maintained, a network layer with the packet receiver and sender and the actual switch as element of the transport layer. This ISO/OSI compliant level-wise structure monitors the network parameters and autonomously adjusts for the size of the neighborhood. It separates the broadcast of the network variables from the actual computation, allowing each to be executed at its own speed. The concept is tested on a re-design of the ILVA architecture and has been shown to handle arbitrary neighborhoods and precision at a comparable size and speed (I node per BlockRAM/multiplier module @220 MHz clock).

关键词： cellular neural network image processing packet switching network system on chip field-programmable gate-array

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Tiled Architecture of a CNN-mostly IP System

Tiled Architecture of a CNN-mostly IP System

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Conference on VLSI Circuits and Systems IV

作者： Spaanenburg, Lambert Malki, Suleyman Lund Univ Elect & Informat Technol Dept S-22100 Lund Sweden

ISBN: (纸本)9780819476371

Multi-core architectures have been popularized with the advent of the IBM CELL. On a finer grain the problems in scheduling multi-cores have already existed in the tiled architectures, such as the EPIC and Da Vinci. It is not easy to evaluate the performance of a schedule on such architecture as historical data are not available. One solution is to compile algorithms for which an optimal schedule is known by analysis. A typical example is an algorithm that is already defined in terms of many collaborating simple nodes, such as a Cellular Neural Network (CNN). A simple node with a local register stack together with a 'rotating wheel' internal communication mechanism has been proposed. Though the basic CNN allows for a tiled implementation of a tiled algorithm on a tiled structure, a practical CNN system will have to disturb this regularity by the additional need for arithmetical and logical operations. Arithmetic operations are needed for instance to accommodate for low-level image processing, while logical operations are needed to fork and merge different data streams without use of the external memory. It is found that the 'rotating wheel' internal communication mechanism still handles such mechanisms without the need for global control. Overall the CNN system provides for a practical network size as implemented on a FPGA, can be easily used as embedded IP and provides a clear benchmark for a multi-core compiler.

关键词： Behavioral Synthesis Algorithm-specific Architecture Cellular Neural Network field-programmable gate-array multi-core benchmark

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Optimization of Input-Constrained Systems

Optimization of Input-Constrained Systems

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Conference on VLSI Circuits and Systems IV

作者： Malki, Suleyman Spaanenburg, Lambert Lund Univ LTH Dept Informat Technol Lund Sweden

ISBN: (纸本)9780819476371

The computational demands of algorithms are rapidly growing. The naive implementation uses extended double-precision floating-point numbers and has therefore extreme difficulties in maintaining real-time performance. For fixed-point numbers, the value representation pushes in two directions (value range and step size) to set the application-dependent word size. In the general case, checking all combinations of all different values on all system inputs will easily become computationally infeasible. Checking corner cases only helps to reduce the combinatorial explosion, as still checking for accuracy and precision to limit word size remains a considerable effort. A range of evolutionary techniques have been tried where the sheer size of the problem withstands an extensive search. When the value range can be limited, the problem becomes tractable and a constructive approach becomes feasible. We propose an approach that is reminiscent of the *** logic minimization procedure. Next to the conjunctive search as popular in Boolean minimization, we investigate the disjunctive approach that starts from a presumed minimal word size. To eliminate the occurrence of anomalies, this still has to be checked for larger word sizes. The procedure has initially been implemented using Java and Mat lab. We have applied the above procedure to feed-forward and to cellular neural networks (CNN) as typical examples of input-constrained systems. In the case of hole-filling by means of a CNN, we find that the 1461 different coefficient sets can be reduced to 360, each giving robust behaviour on 7-bits internal words.

关键词： Behavioural Synthesis Algorithm-specific Architecture Fixed Number Representation field-programmable gate-array

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Natural learning of neural networks by reconfiguration

Natural learning of neural networks by reconfiguration

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Conference on Bioengineered and Bioinspired Systems

作者： Spaanenburg, L Alberts, R Slump, CH vanderZwaag, BJ Lund Univ S-22100 Lund Sweden

ISBN: (纸本)0819449792

The communicational and computational demands of neural networks are hard to satisfy in a digital technology. Temporal computing addresses this problem by iteration, but leaves a slow network. Spatial computing only became an option with the coming of modem FPGA devices. The paper provides two examples. First the balance between area and time is discussed on the realization of a modular feed-forward network. Second, the design of real-time image processing through a Cellular Neural Network is treated. In both examples, reconfiguration can be applied to provide for a natural and transparent support of learning.

关键词： field-programmable gate-array reconfiguration modularity feed-forward neural network cellular neural network temporal computing spatial computing wave computing

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Artificial life goes 'in silico'

Artificial life goes 'in silico'

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IEEE International Conference on Computational Intelligence for Measurement Systems and Applications

作者： Spaanenburg, L Malki, S Lund Univ Dept Informat Technol S-22100 Lund Sweden

ISBN: (纸本)0780390253

The paper reviews a number of Cellular Neural Network implementations on a field-programmable gate-Arraly. It illustrates experimentally, how these implementations can be used to measure from images or to create dynamic, autonomous processes that facilitate measurements within topographic maps. Applications range from image understanding to robot navigation.

关键词： Cellular Neural Network image processing packet switch network system on chip field-programmable gate-array

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Early prototyping and testing of CERN LHC CMS high-granularity calorimeter slow-control system 33

Early prototyping and testing of CERN LHC CMS high-granulari...

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33rd IEEE International Workshop on Rapid System Prototyping (RSP) - Shortening the Path from Specification to Prototype

作者： Rosado, Martim Mallios, Stavros Tomas, Pedro Roma, Nuno David, Andre CERN CMS Collaborat Geneva Switzerland Univ Lisbon Inst Super Tecn INESC ID Lisbon Portugal

ISBN: (纸本)9798350398519

The Compact Muon Solenoid (CMS) highgranularity calorimeter (HGCAL) upgrade for CERN's Large Hadron Collider (LHC) high-luminosity phase is a detector with more than 6 million channels that will provide precise sensing and measurement of position, timing, and energy of the particles produced in the collisions of the beams. The HGCAL electronics are a large and complex set of processing systems split into frontend and back-end. The front-end, located in the experimental cavern, consists of approximate to 150 thousand radiation tolerant ASICs. The high-density FPGA-based back-end is housed away from the radiation area in a set of Advanced Telecommunications Computing Architecture (ATCA) boards and crates hosting approximate to 100 FPGAs. Each ATCA back-end board will comprise one (or two) FPGAs, managing up to approximate to 120 optical links, each providing a transmission rate of 10.24 Gb/s between the back-end and the front-end electronics. Each back-end FPGA is responsible for configuring and monitoring up to approximate to 3500 front-end ASICs and will be controlled by software running on a back-end MPSoC that provides the entry point for the whole control procedure. This paper presents the design and implementation of the prototyping infrastructure deployed to test and validate the slow-control block of the HGCAL back-end electronics, together with the related interfaces with the controller MPSoC and the front-end transceiver ASICs. The required functionalities have been validated with a ZCU102 Xilinx Ultrascale+ development board, which emulated the back-end elements that are still under development and not yet available for this comprehensive test. This development board was connected to other custom ASIC development boards via optical links, emulating the front-end side of the system, also still under development. Besides providing reliable testing and validation of the operation of the whole infrastructure, the prototyping platform also allowed to attain the

关键词： Fast Prototyping System Emulation Testing and Validation field-programmable gate-array

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3D-design exploration of CNN algorithms

3D-design exploration of CNN algorithms

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Conference on VLSI Circuits and Systems V

作者： Spaanenburg, Lambert Malki, Suleyman Lund Univ Dept EIT S-22100 Lund Sweden

ISBN: (纸本)9780819486561

Multi-dimensional algorithms are hard to implement on classical platforms. Pipelining may exploit instruction-level parallelism, but not in the presence of simultaneous data;threads optimize only within the given restrictions. Tiled architectures do add a dimension to the solution space. With locally a large register store, data parallelism is handled, but only to a dimension. 3-D technologies are meant to add a dimension in the realization. Applied on the device level, it makes each computational node smaller. The interconnections become shorter and hence the network will be condensed. Such advantages will be easily lost at higher implementation levels unless 3-D technologies as multi-cores or chip stacking are also introduced. 3-D technologies scale in space, where (partial) reconfiguration scales in time. The optimal selection over the various implementation levels is algorithm dependent. The paper discusses such principles while applied on the scaling of cellular neural networks (CNN). It illustrates how stacking of reconfigurable chips supports many algorithmic requirements in a defect-insensitive manner. Further the paper explores the potential of chip stacking for multi-modal implementations in a reconfigurable approach to heterogeneous architectures for algorithm domains.

关键词： Behavioral Synthesis Algorithm-specific Architecture Cellular Neural Network field-programmable gate-array multi-core benchmark

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Power Characterization of A Gbit/s FPGA Convolutional LDPC Decoder

Power Characterization of A Gbit/s FPGA Convolutional LDPC D...

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IEEE Workshop on Signal Processing Systems (SiPS)

作者： Li, Si-Yun J. Brandon, Tyler L. Elliott, Duncan G. Gaudet, Vincent C. Univ Waterloo Dept Elect & Comp Engn Waterloo ON N2L 3G1 Canada Univ Alberta Dept Elect & Comp Eng Edmonton AB T6G 2M7 Canada

ISBN: (纸本)9780769548562;9781467329866

In this paper, we present an FPGA implementation of parallel-node low-density-parity-check convolutional-code encoder and decoder. A 2.4 Gb/s rate-1/2 (3, 6) LDPC convolutional-code encoder and decoder were implemented on an Altera development and education board (DE4). Detailed power measurements of the FPGA board for various configurations of the design have been conducted to characterize the power consumption of the decoder module. For a E-b/N-o of 5 dB, the decoder with 9 processor cores (pipelined decoder iteration stages) has a bit-error-rate performance of 10(-10), and achieves an energy-per-coded-bit of 1.683 nJ. The increase in E-b/N-o can effectively reduce the decoder power and energy-per-coded-bit for configurations with 5 or more processor cores for E-b/N-o < 5 dB. The incremental decoder power cost and incremental energy-per-coded-bit also hold a linearly decreasing trend for each additional processor core.

关键词： Capacity-approaching codes low-density parity-check codes field-programmable gate-array power measurement

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Power-driven FPGA to ASIC conversion

Power-driven FPGA to ASIC conversion

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Conference on VLSI Circuits and Systems III

作者： Fang, WenHai Spaanenburg, Lambert SwitchCore AB Emdalavagen 18 Lund Sweden Lund Univ Dept Informat Technol Lund Sweden

ISBN: (纸本)9780819467188

gate arrays are often presented as a convenient means for ASIC prototyping. Obviously, they can both perform the same function and therefore be built from the same behavioral description. Design development implies a process of subsequent parameter bindings, leaving steadily less freedom for the remaining implementation choices. On the other hand, the ASIC offers more place & route freedom than the gate array. Hence it is commonly suggested that an optimal prototype will always have an acceptable ASIC realization. But this does not make the gate array an easy stepping-stone in ASIC development. Differences in platform technology induce a different structural sugaring to achieve a reasonable implementation. This cannot easily be ported, unless the implementation is developed while keeping the restrictions for the other technology in mind. Such implies a number of scaling rules to be the foundation of the design transformation process. This paper looks into the platform commonalities of field-programmable gate-arrays and standard-cell ASICs from fundamental physical principles. These basic considerations are then related to show how the area and speed restrictions in the logic synthesis can be applied to carry power efficient designs efficiently from prototype to realization. This is illustrated in the design of the SNOW-2 encryption core, where a consistent 38% power reduction is achieved.

关键词： application-specific integrated circuit field-programmable gate-array computational energy dynamic power dissipation encryption

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