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Analysis on parallel implementations of fixed-complexity sphere decoder

Science China(Information Sciences) 2013年第4期56卷 155-165页

作者： WU Bin MASERA Guido VLSI Lab Dipartimento di ElettronicaPolitecnico di TorinoTorino 10129Italy

sphere decoders are widely investigated for the implementation of multiple-input multiple-output(MIMO) *** a large number of sphere decoding algorithms,the fixed-complexity sphere decoder(FSD) exhibits remarkable advantages in terms of constant throughput and high flexibility of parallel *** this paper,we present a four-nodes-per-cycle parallel FSD architecture with balanced performance and hardware complexity,and several examples of VLSI implementation for different types of modulation and both real and complex signal *** aspects and architecture details are analyzed in order to present a hardware-level perspective of the FSD *** a variety of performance-complexity trade-offs are *** implementation results show that the proposed parallel FSD architecture is highly efficient and flexible,especially in the complex signal model.

关键词： MIMO detection fixed-complexity sphere decoder parallel architecture VLSI implementation

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Energy-Efficient Adaptive Modulated fixed-complexity sphere decoder

Energy-Efficient Adaptive Modulated Fixed-Complexity Sphere ...

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35th IEEE Workshop on Signal Processing Systems (IEEE SiPS)

作者： Wu, Yun McAllister, John Heriot Watt Univ Sch Engn & Phys Sci Edinburgh Midlothian Scotland Queens Univ Belfast Sch Elect Elect Engn & Comp Sci Belfast Antrim North Ireland

ISBN: (纸本)9781665401449

fixed-complexity sphere decoder (FSD) is an quasi-optimal detector for Multiple-Input Multiple-Output (MIMO) system which is a hardware-friendly parallel tree-search customised to the modulation and antenna scheme employed. However, it is not able to adapt its behaviour for various modulation and antenna schemes, as demanded by modern wireless standard. This restricts its usage in modern adaptive MIMO systems. This paper proposes a solution to this problem. A configurable FSD structure in proposed where normalized higher order modulation schemes can accommodate lower ones. By exploiting clock-gating, FSD of all modulation schemes is equally trimmed to allow power savings of over 30% when implementing on Field Programmable Gate Array (FPGA). This architecture enables the facility to balance the power consumptions with compatible information rate in dynamic, adaptive MIMO communications environments.

关键词： Adaptive Modulation fixed-complexity sphere decoder Multiple-Input Multiple-Output Field Programmable Gate Array

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A Novel VLSI Architecture of fixed-complexity sphere decoder

A Novel VLSI Architecture of Fixed-complexity Sphere Decoder

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13th Euromicro Conference on Digital System Design on Architectures, Methods and Tools

作者： Wu, Bin Masera, Guido Politecn Torino Dept Elect VLSI Lab Turin Italy

ISBN: (纸本)9780769541716

fixed-complexity sphere decoder (FSD) is a recently proposed technique for multiple-input multiple-output (MIMO) detection. It has several outstanding features such as constant throughput and large potential parallelism, which makes it suitable for efficient VLSI implementation. However, to our best knowledge, no VLSI implementation of FSD has been reported in the literature, although some FPGA prototypes of FSD with pipeline architecture have been developed. These solutions achieve very high throughput but at very high cost of hardware resources, making them impractical in real applications. In this paper, we present a novel four-nodes-per-cycle parallel architecture of FSD, with a breadth-first processing that allows for short critical path. The implementation achieves a throughput of 213.3 Mbps at 400 MHz clock frequency, at a cost of 0.18 mm(2) Silicon area on 0.13 mu m CMOS technology. The proposed solution is much more economical compared with the existing FPGA implementations, and very suitable for practical applications because of its balanced performance and hardware complexity;moreover it has the flexibility to be expanded into an eight-nodes-per-cycle version in order to double the throughput.

关键词： MIMO detection fixed-complexity sphere decoder constant throughput parallel architecture breadth-first processing VLSI implementation

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Near-ML MIMO Detection Algorithm With LR-Aided fixed-complexity Tree Searching

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IEEE COMMUNICATIONS LETTERS 2014年第12期18卷 2221-2224页

作者： Kim, Hyunsub Park, Jangyong Lee, Hyukyeon Kim, Jaeseok Yonsei Univ Dept Elect & Elect Engn Seoul 120749 South Korea

In this paper, we propose a low-complexity multiple-input multiple-output (MIMO) detection algorithm with lattice-reduction-aided fixed-complexity tree searching which is motivated by the fixed-complexity sphere decoder (FSD). As the proposed scheme generates a fixed tree whose size is much smaller than that of the full expansion in the FSD, the computational complexity is reduced considerably. Nevertheless, the proposed scheme achieves a near-maximum-likelihood (ML) performance with a large number of transmit antennas and a high-order modulation. The experimental results demonstrate that the performance degradation of the proposed scheme is less than 0.5 dB at the bit error rate (BER) of 10(-5) for a 8 x 8 MIMO system with 256 QAM. Also, the proposed method reduces the complexity to about 1.23% of the corresponding FSD complexity.

关键词： MIMO lattice reduction tree searching fixed-complexity sphere decoder

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Low complexity Soft-Output Signal Detector for Spatial-Multiplexing MIMO System

Low Complexity Soft-Output Signal Detector for Spatial-Multi...

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22nd IEEE International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC)

作者： Liu, Liang Lofgren, Johan Nilsson, Peter Lund Univ Dept Elect & Informat Technol S-22100 Lund Sweden

ISBN: (纸本)9781457713484

This paper presents a cost-efficient soft-output signal detector design solution targeting on the spatial-multiplexing MIMO system. The detector achieves low hardware cost and near-optimal detection performance based on the modification to the fixed-complexity sphere decoder (FSD) using several implementation-oriented algorithm-level improvements, which are early-pruning with polygon-shaped constraint, symbol-level bit-flipping, and l(1)-norm approximation. To evaluate the proposed method, we implement the MIMO detector in a 65-nm standard V-T CMOS technology. The core area is 0.14 mm(2) with 69 K equivalent gates, representing a 60% hardware-resource saving to the state-of-the-art in the open literature. The detecting throughput is up to 1.5Gb/s at 250-MHz clock frequency and 1.2-V supply. The normalized energy consumption of 36.4 pJ/b is shown to be the most energy-efficient design compared with other soft-output detectors.

关键词： Bit error rate CMOS integrated circuits CMOS technology complexity theory Decoding Detectors MIMO MIMO communication Throughput Vectors approximation theory clock frequency communication complexity decoding equivalent gate fixed-complexity sphere decoder frequency 250 MHz hardware-resource implementation-oriented algorithm-level improvement l1-norm approximation low complexity soft-output signal detector near-optimal detection performance polygon-shaped constraint signal detection size 65 nm space division multiplexing spatial-multiplexing MIMO system symbol-level bit-flipping

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