A parallel switched-current AID converter is presented. Eight time-interleaved snitched-current ADCs operating at 4 M sample/s are used to increase the sampling rate. With channel compensation, the measured SFDR is &g...
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A parallel switched-current AID converter is presented. Eight time-interleaved snitched-current ADCs operating at 4 M sample/s are used to increase the sampling rate. With channel compensation, the measured SFDR is > 50 dB at 32 M sample/s with f(in) = 1.13 MHz. The performance of this experimental design is limited by noise and a fixed-pattern timing error that is not removed by the compensation algorithm.
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