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Conference on Advanced Signal Processing Algorithms, Architectures and Implementations XII

作者： Moon, YS Luk, FT Ho, HC Tang, TY Chan, KC Leung, CW Chinese Univ Hong Kong Dept Comp Sci & Engn Shatin Hong Kong Peoples R China

ISBN: (纸本)0819445584

Mobile devices use embedded processors with low computing capabilities to reduce power consumption. Since floating-point arithmetic units are power hungry, computationally intensive jobs must be accomplished with either digital signal processors or hardware co-processors. In this paper, we propose to perform fixed-point arithmetic on an integer hardware unit. We illustrate the advantages of our approach by implementing fingerprint verification on mobile devices.

关键词： embedded system fixed-point arithmetic fingerprint verification smart card personal digital assistant

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fixed-point arithmetic Modeled in B Software Using Reals

Fixed-Point Arithmetic Modeled in B Software Using Reals

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4th International Conference on Abstract State Machines, Alloy, B, TLA,VDM, and Z (ABZ)

作者： Guery, Jerome Rolland, Olivier Rehm, Joris ClearSy Ave Archimede Les Pleiades 3Bat A F-13857 Aix En Provence 3 France ALSTOM Transport F-93482 St Ouen France

ISBN: (纸本)9783662436523;9783662436516

This paper demonstrates how to introduce a fixed point arithmetic in software developed with the classical B method. The properties of this arithmetic are specified with real numbers in the AtelierB formal tool and linked to an implementation written in Ada programming language. This study has been conducted to control the loss of precision and possible overflow due to the use of fixed point arithmetic in the critical software part of a communication based train control system.

关键词： formal method B method fixed-point arithmetic

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fixed-point arithmetic for Implementing Massive MIMO Systems 24

Fixed-Point Arithmetic for Implementing Massive MIMO Systems

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24th International Conference on Advanced Communication Technology (ICACT) - Artificial Intelligence Technologies toward Cybersecurity

作者： Tian, Mi Sima, Mihai McGuire, Michael Univ Victoria Dept Elect & Comp Engn POB 1700 Stn CSC Victoria BC V8W 2Y2 Canada

ISBN: (纸本)9791188428090

Massive MIMO base stations are expensive to build due to the requirement for a large number of RF transceivers and high-resolution analog-to-digital converters. A way to reduce the implementation cost is to build the base stations with inexpensive hardware, resulting in the received signals to be coarsely quantized. First, the required signal power needed to achieve different receiver Bit-Error Rate (BER) levels is determined, as well as the extra signal power needed due to the quantization for given BER levels. To implement the data detection and decoding process in real time, fixed-point arithmetic with reduced precision is used. This article also reports the minimum wordlength needed to maintain the BER at acceptable levels. Specifically, the eigenvalue decomposition, which is the most computationally demanding portion of the receiver algorithm, can be calculated with wordlengths of 7 and 10 bits for eigenvectors and eigenvalues, respectively.

关键词： Massive MIMO fixed-point arithmetic

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fixed-point arithmetic Error Analysis of Sparse LU Decomposition on FPGAs

Fixed-Point Arithmetic Error Analysis of Sparse LU Decomposi...

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International Symposium on Signals, Circuits and Systems (ISSCS)

作者： Feali, Mohammad Saeed Ahmadi, Arash Hamidi, Abdosamad Ahmadi, Majid Razi Univ Dept Elect Engn Kermanshah Iran Univ Windsor Dept Elect & Comp Engn Windsor ON Canada

ISBN: (纸本)9781538606742

FPGAs are becoming an attractive platform for accelerating many computations including scientific applications. These applications demand high performance and high precision arithmetic. Decomposition of a matrix into lower and upper triangular matrices (LU decomposition) is a vital part of many scientific and engineering applications. This paper evaluates the accuracy of a fixed-point LU decomposition based on FPGA. fixed-point architecture of LU decomposition is implemented on FPGA. Then several matrices with different sizes and random elements are decomposed using this architecture by various word-lengths. Using random matrices and different word-lengths, descriptive analysis of error is performed.

关键词： fixed-point arithmetic LU Decomposition FPGA Error Analysis

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ROUNDOFF-ERROR REDUCTION FOR EVALUATION OF A FUNCTION BY POLYNOMIAL-APPROXIMATION WITH ERROR FEEDBACK IN fixed-point arithmetic

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IEEE TRANSACTIONS ON SIGNAL PROCESSING 1993年第5期41卷 1953-1955页

作者： MIKAMI, N KOBAYASHI, M YOKOYAMA, Y Department of Information and Computer Science University of Industrial Technology Sagamihara Kanagawa Japan

Error feedback (EFB) is a useful technique to reduce the roundoff errors in recursive fixed-point digital filters. This correspondence shows that evaluation of a polynomial by Hornor's method is equivalent to a first-order recursive filter and EFB is a useful technique to reduce the roundoff errors that occur in evaluating a function by polynomial approximation.

关键词： Polynomials Feedback Digital filters Roundoff errors Signal processing algorithms fixed-point arithmetic Quantization Computer errors Electronic switching systems Equations

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NEW CRITERIA FOR ASYMPTOTIC STABILITY OF ONE-DIMENSIONAL AND MULTIDIMENSIONAL STATE-SPACE DIGITAL-FILTERS IN fixed-point arithmetic

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IEEE TRANSACTIONS ON SIGNAL PROCESSING 1994年第1期42卷 46-53页

作者： LECLERE, LJ BAUER, PH ERICSSON COMMUN INC VILLE MT ROYALPQCANADA

This paper addresses the problem of global asymptotic stability of one-dimensional (1-D) and multidimensional (m-D) digital filters with any combination of overflow and quantization nonlinearities. The stability analysis is carried out using 1-D and m-D state-space representations. The approach introduced in this paper allows one to determine the stability behavior of single-input single-output systems with overflow and quantization nonlinearities. The new criteria, based on previous stability results of digital filters with quantization schemes, are applicable to all arithmetic schemes. For the first time, results concerning general state variable representations of 1-D and m-D digital filters with the naturally occurring combination of two's complement truncation quantization and overflow are reported. Furthermore, significantly improved stability regions are obtained for digital filters with roundoff nonlinearities.

关键词： Asymptotic stability Multidimensional systems Digital filters Quantization Stability criteria Digital arithmetic Testing fixed-point arithmetic Stability analysis

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Augmented Lagrangian optimization under fixed-point arithmetic

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AUTOMATICA 2020年 122卷 109218-109218页

作者： Zhang, Yan Zavlanos, Michael M. Duke Univ Mech Engn & Mat Sci Durham NC 27708 USA

In this paper, we propose an inexact Augmented Lagrangian Method (ALM) for the optimization of convex and nonsmooth objective functions subject to linear equality constraints and box constraints where errors are due to fixed-point data. To prevent data overflow we also introduce a projection operation in the multiplier update. We analyze theoretically the proposed algorithm and provide convergence rate results and bounds on the accuracy of the optimal solution. Since iterative methods are often needed to solve the primal subproblem in ALM, we also propose an early stopping criterion that is simple to implement on embedded platforms, can be used for problems that are not strongly convex, and guarantees the precision of the primal update. To the best of our knowledge, this is the first fixed-point ALM that can handle non-smooth problems, data overflow, and can efficiently and systematically utilize iterative solvers in the primal update. Numerical simulation studies on a logistic regression problem are presented that illustrate the proposed method. (c) 2020 Elsevier Ltd. All rights reserved.

关键词： Convex optimization Augmented Lagrangian Method Embedded systems fixed-point arithmetic

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Implementation of Resonant Controllers and Filters in fixed-point arithmetic

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS 2009年第4期56卷 1273-1281页

作者： Harnefors, Lennart ABB Power Syst HVDC S-77180 Ludvika Sweden

Resonant controllers and filters are useful in voltage-source-converter control systems. Although the trend is toward implementation in floating-point arithmetic, fixed-point arithmetic is still of interest, but requires much greater care in the algorithm design. This paper covers some important issues, namely, choice of structure, design formulas, scaling, sensitivity, quantization-noise amplification, and suppression of overflow limit cycles. The results presented should be particularly helpful as design guidelines to practical engineers in a situation where one often resorts to trial and error.

关键词： Converter control filters fixed-point arithmetic resonators

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Formalization of fixed-point arithmetic in HOL

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FORMAL METHODS IN SYSTEM DESIGN 2005年第1-2期27卷 173-200页

作者： Akbarpour, B Tahar, S Dekdouk, A Concordia Univ Dept Elect & Comp Engn Montreal PQ H3G 1M8 Canada

This paper addresses the formalization in higher-order logic of fixed-point arithmetic. We encoded the fixed-point number system and specified the different quantization modes in fixed-point arithmetic such as the directed and even quantization modes. We also considered the formalization of exceptions detection and their handling like overflow and invalid operation. An error analysis is then performed to check the correctness of the quantized result after carrying out basic arithmetic operations, such as addition, subtraction, multiplication and division against their mathematical counterparts. Finally, we showed by an example how this formalization can be used to enable the verification of the transition from floating-point to fixed-point algorithmic level in the signal processing design flow.

关键词： fixed-point arithmetic floating-point arithmetic theorem-proving HOL

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Parametrizable fixed-point arithmetic for HIL With Small Simulation Steps

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IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS 2019年第4期7卷 2467-2475页

作者： Sanchez, Alberto de Castro, Angel Garrido, Javier Univ Autonoma Madrid Elect & Commun Technol Dept E-28049 Madrid Spain

Hardware-in-the-loop (HIL) techniques are increasingly used for test purposes because of their advantages over classical simulations. Field-programmable gate arrays (FPGAs) are becoming popular in HIL systems because of their parallel computing capabilities. In most cases, FPGAs are mainly used for signal processing, such as input pulsewidth modulation sampling and conditioning, while there are also processors to model the system. However, there are other HIL systems that implement the model in the FPGA. For FPGA implementation and regarding the arithmetics, there are two main possibilities: fixed-point and floating-point. fixed-point is the best choice only when real-time simulations with small simulation steps are needed, while floating-point is the common choice because of its flexibility and ease of use. This paper presents a novel hybrid arithmetic for FPGAs called parametrizable fixed-point which takes advantage of both arithmetics as the internal operations are accomplished using simple signed integers, while the point location of the variables can be adjusted as necessary without redesigning the model of the plant. The experimental results show that a buck converter can be modeled using this novel arithmetic with a simulation step below 20 ns. Besides, the experiments prove that the proposed model can be adjusted to any set of values (voltages, currents, capacitances, and so on.) keeping its accuracy without resynthesizing, showing the big advantage over the fixed-point arithmetic.

关键词： Mathematical model Numerical models Field programmable gate arrays Tools Pulse width modulation Inductors Power electronics Emulation field-programmable gate array (FPGA) fixed-point arithmetic floating-point arithmetic

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