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检索条件"主题词=fixed-point arithmetic"

共 774 条记录，以下是21-30 订阅

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RELIABLE IMPLEMENTATION OF LINEAR FILTERS WITH fixed-point arithmetic

RELIABLE IMPLEMENTATION OF LINEAR FILTERS WITH FIXED-POINT A...

引用

IEEE Workshop on Signal Processing Systems (SiPS)

作者： Hilaire, Thibault Lopez, Benoit Univ Paris 06 LIP6 Paris France

ISBN: (纸本)9781467362382

This article deals with the implementation of linear filters or controllers with fixed-point arithmetic. The finite precision of the computations and the roundoff errors induced may have an important impact on the numerical behavior of the implemented system. Moreover, the fixed-point transformation is a time consuming and error-prone task, specially with the objective of minimizing the quantization impact. Based on a formalism able to describe every structure of linear filters/controllers, this paper proposes an automatic method to generate fixed-point version of the inputs-to-outputs algorithm and an analysis of the global error added on the output. An example illustrates the approach.

关键词： fixed-point arithmetic error analysis filter implementation code generation

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FPGA hardware linear regression implementation using fixed-point arithmetic 19

FPGA hardware linear regression implementation using fixed-p...

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32nd Symposium on Integrated Circuits and Systems Design (SBCCI)

作者： Pedrobon Ferreira, Willian de Assis Grout, Ian Rodrigues da Silva, Alexandre Cesar Sao Paulo State Univ UNESP Scholl Engn Ilha Solteira Brazil Univ Limerick Dept Elect & Comp Engn Limerick Ireland

ISBN: (纸本)9781450368445

In this paper, a hardware design based on the field programmable gate array (FPGA) to implement a linear regression algorithm is presented. The arithmetic operations were optimized by applying a fixed-point number representation for all hardware based computations. A floating-point number training data point was initially created and stored in a personal computer (PC) which was then converted to fixed-point representation and transmitted to the FPGA via a serial communication link. With the proposed VHDL design description synthesized and implemented within the FPGA, the custom hardware architecture performs the linear regression algorithm based on matrix algebra considering a fixed size training data point set. To validate the hardware fixed-point arithmetic operations, the same algorithm was implemented in the Python language and the results of the two computation approaches were compared. The power consumption of the proposed embedded FPGA system was estimated to be 136.82 mW.

关键词： Machine learning linear regression hardware fixed-point arithmetic FPGA

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ACCURATE PARAMETER GENERATION USING fixed-point arithmetic FOR EMBEDDED HMM-BASED SPEECH SYNTHESIZERS

ACCURATE PARAMETER GENERATION USING FIXED-POINT ARITHMETIC F...

引用

IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP)

作者： Nishizawa, Nobuyuki Kato, Tsuneo KDDI R and D Laboratories Inc. Japan

ISBN: (纸本)9781457705397

Parameter trajectory generation for HMM-based speech synthesis is practically achieved using only fixed-point arithmetic with 32-bit integers. Since processors for embedded devices often provide no hardware-based floating-point number processor, a speech synthesizer using only fixed-point arithmetic is necessary for such devices. In this study, a new method to reduce rounding errors is introduced, as well as optimizing value scaling, and the generation of F-0 trajectory is discussed. The experimental results indicated that RMSE in a logarithmic scale of F-0 can be reduced down to approximately 0.04 semitones (1 semitone = 1/12 octaves) by the proposed method even where a 2-bit margin was arranged to avoid calculation overflow. An extension for trajectories considering the global variance (GV) using the basic program for trajectories without consideration of GV is also introduced. The extension method reduces required iteration counts to 5 for 0.05-semitone RMSE comparable to the converged results of the conventional method.

关键词： HMM-based speech synthesis fixed-point arithmetic embedded devices global variance

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Massive MIMO in fixed-point arithmetic 23

Massive MIMO in Fixed-Point Arithmetic

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23rd International Conference on Advanced Communications Technology (ICACT) - On-Line security in Pandemic Era

作者： Tian, Mi Sima, Mihai McGuire, Michael Univ Victoria Dept Elect & Comp Engn POB 1700 Stn CSC Victoria BC V8W 2Y2 Canada

ISBN: (纸本)9791188428069

Massive MIMO base stations are expensive to build due to the requirement for a large number of RF transceivers and high-resolution analog-to-digital converters. A way to reduce the implementation cost is to build the base stations with inexpensive hardware, resulting in the received signals to be coarsely quantized. To implement the data detection and decoding process in real time, fixed-point arithmetic with reduced precision is used. This article reports the minimum wordlength needed to maintain the Bit-Error Rate (BER) at acceptable levels. Specitically, the eigenvalue decomposition, which is the most computationally demanding portion of the receiver algorithm, can be calculated with wordlengths of 7 and 10 bits for eigenvectors and eigenvalues, respectively.

关键词： Massive MIMO fixed-point arithmetic

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Issues with rounding in the GCC implementation of the ISO 18037:2008 standard fixed-point arithmetic 27

Issues with rounding in the GCC implementation of the ISO 18...

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27th IEEE Symposium on Computer arithmetic (ARITH)

作者： Mikaitis, Mantas Univ Manchester Dept Math Manchester Lancs England

ISBN: (数字)9781728171203

ISBN: (纸本)9781728171203

We describe various issues caused by the lack of round-to-nearest mode in the gcc compiler implementation of the fixed-point arithmetic data types and operations. We demonstrate that round-to-nearest is not performed in the conversion of constants, conversion from one numerical type to a less precise type and results of multiplications. Furthermore, we show that mixed-precision operations in fixed-point arithmetic lose precision on arguments, even before carrying out arithmetic operations. The ISO 18037:2008 standard was created to standardize C language extensions, including fixed-point arithmetic, for embedded systems. Embedded systems are usually based on ARM processors, of which approximately 100 billion have been manufactured by now. Therefore, the observations about numerical issues that we discuss in this paper can be rather dangerous and are important to address, given the wide ranging type of applications that these embedded systems are running.

关键词： fixed-point arithmetic rounding ISO 18037:2008

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Fault Detection of Surveillance Camera Using fixed-point arithmetic Operations 1

Fault Detection of Surveillance Camera Using Fixed-point Ari...

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1st IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW)

作者： Zeng, Yi-Chong Yu, Cheng-Juei Chang, Wen-Tsung Inst Informat Ind Taipei Taiwan

ISBN: (纸本)9781479948512

In this paper, we propose fixed-point operations to measure frame quality assessments as features, and then the computed features are analyzed for fault detection of surveillance camera. The proposed operations include fractional addition, fractional multiplication, and fractional division. Two kinds of quality assessments are employed namely structure similarity and average color. The proposed fault detection scheme analyzes the features using rule-based determination, discriminates corrupted frames among normal ones, and determines whether surveillance camera is normal or not. The experiment results will demonstrate that our scheme is efficient in fault detection of surveillance camera based on fixed-point operations.

关键词： Accuracy Cameras Color Fault detection Feature extraction fixed-point arithmetic Surveillance

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Wave Computer Core Using fixed-point arithmetic

Wave Computer Core Using Fixed-point Arithmetic

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Karakaya, Baris Yeniceri, Ramazan Yalcin, Mustak E. Firat Univ Dept Elect Elect Engn TR-23119 Elazig Turkey Istanbul Tech Univ Dept Elect & Commun Engn TR-34469 Istanbul Maslak Turkey

ISBN: (纸本)9781479983919

In this paper, success on cellular nonlinear network emulator core that generates active waves such as autowaves and traveling waves is intended. This wave computer core has 4 x 4 parallel processing units. Cellular nonlinear network in this study has 16;384 nodes arranged in 128 x 128 normal grid form. The evolution algorithm of the network is executed by the hardware implemented on a Xilinx XC2VP30-FF896 FPGA chip using fixed-point arithmetic. The FPGA-based platform has an on-line monitor output in order to observe active wave evolution and a host computer in order to program the network. Using fixed-point number format rather than floating-point number format has some advantages in the sense of speed and resource usage. The implementation in this study can be adapted to observe Doppler Effect on traveling waves and autowaves.

关键词： Cellular Neural/Nonlinear Networks (CNNs) Wave Computer Field Programmable Gate Array (FPGA) fixed-point arithmetic

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Tight Error Analysis in fixed-point arithmetic 16th

Tight Error Analysis in Fixed-Point Arithmetic

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16th International Conference on Integrated Formal Methods (IFM)

作者： Simic, Stella Bemporad, Alberto Inverso, Omar Tribastone, Mirco IMT Sch Adv Studies Lucca Italy Gran Sasso Sci Inst Laquila Italy

ISBN: (纸本)9783030634612;9783030634605

We consider the problem of estimating the numerical accuracy of programs with operations in fixed-point arithmetic and variables of arbitrary, mixed precision and possibly non-deterministic value. By applying a set of parameterised rewrite rules, we transform the relevant fragments of the program under consideration into sequences of operations in integer arithmetic over vectors of bits, thereby reducing the problem as to whether the error enclosures in the initial program can ever exceed a given order of magnitude to simple reachability queries on the transformed program. We present a preliminary experimental evaluation of our technique on a particularly complex industrial case study.

关键词： fixed-point arithmetic Static analysis Numerical error analysis Program transformation

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Synthesizing Optimal fixed-point arithmetic for Embedded Signal Processing

Synthesizing Optimal Fixed-Point Arithmetic for Embedded Sig...

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53rd Midwest Symposium on Circuits and Systems (MWSCAS 2010)

作者： Hass, K. Joseph Bucknell Univ Lewisburg PA 17837 USA

ISBN: (纸本)9781424477739

Using fixed-point arithmetic rather than floating-point for data processing can significantly reduce the cost and power consumption of embedded systems. Unfortunately, this also shifts the burden of managing the data representation from run time to compile time, and in many cases the task of compile-time optimization must be done manually. A number of attempts have been made to formalize this process, and fixed-point methods have even been codified into an industry standard for a popular hardware-definition language, VHDL, in recent years. While the standard fixed-point libraries are certainly correct in the strict sense, they overlook an important practical consideration and may often produce results that are far from optimal. This paper discusses methods for maximizing the efficiency of fixed-point operations by careful use of the standard libraries.

关键词： fixed-point arithmetic signal processing fixed point FLOATING pointS Representation of data Runtime Power consumption

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Bit-Precise Verification of Discontinuity Errors Under fixed-point arithmetic 19th

Bit-Precise Verification of Discontinuity Errors Under Fixed...

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19th International Conference on Software Engineering and Formal Methods (SEFM)

作者： Simic, Stella Inverso, Omar Tribastone, Mirco IMT Sch Adv Studies Lucca Italy Gran Sasso Sci Inst Laquila Italy

ISBN: (纸本)9783030921248;9783030921231

Non-integer arithmetic is prone to numerical errors due to the finite representation of numbers. These errors propagate, possibly non-linearly, throughout the variables of a program and can affect its control flow, altering reachability, and thus safety. We consider the problem of rigorous bit-precise numerical accuracy certification of programs in the presence of control structures and operations under fixed-point arithmetic over (non-deterministic) variables of arbitrary, mixed precision. By applying program transformation, we reduce the problem of assessing whether a given error bound can be exceeded in the initial program to a reachability problem in a bit-vector program. We implement our technique as a pre-processing module that integrates seamlessly with an existing mature BMC-based verification workflow. We present an experimental evaluation of our error certification technique on a set of arithmetic routines commonly used in the industry.

关键词： fixed-point arithmetic Control-flow Numerical error Program transformation Discontinuity error Bounded model checking

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