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International Conference on Field Programmable Logic and Applications

作者： C. K. Wong Philip H. W. Leong Department of Computer Science and Engineering Chinese University of Hong Kong Sha Tin Hong Kong China

An improved FPGA implementation of an electronic cochlea filter is presented. We show that by using decimation, the computations of the electronic cochlea can be reduced. Furthermore, employing dual fixed-point arithmetic, gives a significant improvement in signal to noise ratio. A sequential architecture is described which employs pipelined infinite impulse response filter stages. The accuracy, performance and resource utilisation of a number of different implementations are compared

关键词： fixed-point arithmetic IIR filters Cutoff frequency Computer architecture Humans Vibrations Signal processing Speech recognition Hardware Auditory system

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A Decoder for Lvcsr Based on fixed-point arithmetic

A Decoder for Lvcsr Based on Fixed-Point Arithmetic

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International Conference on Acoustics, Speech, and Signal Processing (ICASSP)

作者： E. Bocchieri D. Blewett AT and T Research Laboratories Florham Park NJ USA

The increasing computational power of embedded CPU's motivates the fixed-point implementation of highly accurate large-vocabulary continuous-speech (LVCSR) algorithms, to achieve the same performance on the device as on the server. We report on methods for the fixed-point implementation of the frame-synchronous beam-search Viterbi decoder, N-grams language models, and HMM likelihood computation. This fixed-point recognizer is as accurate as our best floating-point recognizer in several LVCSR experiments on the DARPA switch-board task and on an AT&T proprietary task, with different types of acoustic front-ends and HMM's. We also present experiments on the DARPA resource management task using the StrongARM-1100 206 MHz CPU, where the fixed-point implementation enables real-time performance: the floating-point recognizer, with floating-point software emulation, is 50 times slower for the same accuracy

关键词： Decoding fixed-point arithmetic Hidden Markov models Costs Context modeling Viterbi algorithm Resource management Application software Telephony Speech recognition

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Evaluation of Computational Cost and Result Accuracy in Design and Efficient Implementation of Log-Mel Spectrogram and MFCC Feature Extraction Using fixed-point arithmetic on FPGA

Evaluation of Computational Cost and Result Accuracy in Desi...

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IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)

作者： Chenyu Zhao Naoya Yamamura Hiroshi Tsutsui Takeo Ohgane Graduate School of Information Science and Technology Hokkaido University Faculty of Information Science and Technology Hokkaido University

ISBN: (数字)9798350389210

ISBN: (纸本)9798350389227

Mel-frequency cepstral coefficients (MFCCs) are essential features in audio processing, aligning with human auditory perception and are used in applications such as speech recognition, speaker identification, and audio compression. Despite their benefits, the computational complexity of MFCCs poses challenges for real-time applications and embedded systems. Field-programmable gate arrays (FPGAs) offer a solution with their parallel processing capabilities and efficient handling of complex arithmetic operations. This paper presents an optimized implementation of the MFCC algorithm on an FPGA, focusing on computational cost and resulting accuracy. Our key strategies include using fixed-point arithmetic to reduce computational complexity and resource usage. We compare software and hardware implementations of the fast Fourier transform (FFT) to demonstrate the advantages of FPGA-based acceleration. The system is designed for high customization, allowing adaptation to various application requirements. Experimental results explore both the speed of fixed-point arithmetic and the processing results compared to the librosa library in Python, validating the data accuracy under fixed-point operations. These findings provide a foundation for integrating audio feature extraction in system-on-a-chips (SoCs) for various application scenarios.

关键词： Accuracy Fast Fourier transforms Feature extraction Real-time systems Hardware Computational efficiency Mel frequency cepstral coefficient Computational complexity Field programmable gate arrays fixed-point arithmetic

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A steady-state analysis of adaptive notch filters realized with fixed-point arithmetic

A steady-state analysis of adaptive notch filters realized w...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： S. Nishimura The Department of Computer Scienceence Shimane University Matsue Japan

A mean square error analysis is presented of the steady-state coefficient fluctuation of infinite impulse response (IIR) adaptive notch filters realized with fixed-point arithmetic. The reduction of quantization noise by means of error spectrum shaping is discussed. The variances of coefficient error due to quantization noise are derived in simple closed-form for gradient and normalized gradient algorithms. The results of computer simulations are presented to substantiate the analysis.< >

关键词： Steady-state Adaptive filters IIR filters Quantization Noise shaping Computer errors Mean square error methods Error analysis Fluctuations fixed-point arithmetic

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fixed-point TRUNCATION arithmetic IMPLEMENTATION OF A LINEAR PREDICTION AUTOCORRELATION VOCODER

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IEEE TRANSACTIONS ON ACOUSTICS SPEECH AND SIGNAL PROCESSING 1974年第4期AS22卷 273-282页

作者： MARKEL, JD GRAY, AH SPEECH COMMUN RES LAB SANTA BARBARA CA 93109 USA

The implementation of the Linear Prediction Auto-correlation Vocoder (LPAV) with fixed-point truncation arithmetic is presented. For a speech bandwidth of up to 3.3 kHz, it is possible to implement LPAV with a maximum of 16-bit fixed-point arithmetic, thus allowing for very efficient software simulation on minicomputers or economical hardware implementation on a special purpose computer. The resultant degradation with respect to a floating-point implementation is negligible. The three most critical system components are discussed in detail along with various tradeoffs such as effects on system stability as a function of preemphasis and sampling frequency. The results are also applicable to general finite word length digital filter implementation problems.

关键词： fixed-point arithmetic Autocorrelation Vocoders Speech Bandwidth Computational modeling Computer simulation Microcomputers Economic forecasting Hardware

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Implementing a ΣΔ DAC in fixed point arithmetic

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IEEE SIGNAL PROCESSING MAGAZINE 2006年第6期23卷 66-69页

作者： Engelberg, Shlomo Jerusalem Coll Technol Dept Elect Jerusalem Israel

This paper describes a simple sigma delta (SigmaDelta) digital to analog converter (DAC) that is suitable for use on the simplest of microprocessors to generate constant level or slowly varying control voltages by taking advantage of a SigmaDelta network's intrinsic limit cycle behavior. The paper describes the properties of the converter, and shows that it is inherently stable. It also explains how the user can control the dc level of the DAC's analog output, and discusses the implementation of such a DAC on an industry standard microprocessor

关键词： fixed-point arithmetic Microprocessors Limit-cycles Low pass filters Delta-sigma modulation Digital-analog conversion Voltage control Electrical equipment industry Equations Automata

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A Correctly-Rounded fixed-point-arithmetic Dot-Product Algorithm 27

A Correctly-Rounded Fixed-Point-Arithmetic Dot-Product Algor...

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27th IEEE Symposium on Computer arithmetic (ARITH)

作者： Boldo, Sylvie Gallois-Wong, Diane Hilaire, Thibault Univ Paris Saclay CNRS INRIA Lab Rech Informat F-91405 Orsay France Sorbonne Univ LIP6 UMR 7606 F-75005 Paris France

ISBN: (纸本)9781728171203

Dot products (also called sums of products) are ubiquitous in matrix computations, for instance in signal processing. We are especially interested in digital filters, where they are the core operation. We therefore focus on fixed-point arithmetic, used in embedded systems for time and energy efficiency. Common dot product algorithms ensure faithful rounding. For the sake of accuracy and reproducibility, we want to ensure correct rounding. This article describes an algorithm that computes a correctly-rounded sum of products from inputs whose format is known in advance. This algorithm relies on odd rounding (that is easily implemented in hardware) and comes with a careful proof and some cost analysis.

关键词： Dot Product Sum-of-Products Correct Rounding Odd Rounding fixed-point arithmetic

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Towards hardware ray tracing using fixed point arithmetic

Towards hardware ray tracing using fixed point arithmetic

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IEEE/EG Symposium on Interactive Ray Tracing

作者： Hanika, Johannes Keller, Alexander Univ Ulm D-89069 Ulm Germany

ISBN: (纸本)9781424416295

For realistic image synthesis and many other simulation applications, ray tracing is the only choice to achieve the desired realism and accuracy. Ray tracing has become such an important algorithm that an implementation in hardware is justified and desirable. The first ray tracing hardware realizations have been using floating point and logarithmic arithmetic. While floating point arithmetic requires considerably more logic than integer arithmetic, an implementation in logarithmic arithmetic is much simpler, but still suffers from similar problems. In analogy to rasterization hardware we therefore investigate the use of fixed point arithmetic for ray tracing. Our software implementation and comparisons provide strong evidence that an implementation of ray tracing in hardware using fixed point arithmetic is an efficient and robust choice.

关键词： fixed-point arithmetic Ray tracing Computer hardware Image synthesis FLOATING pointS software implementation

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Bit-error rate performance of a two-user CDMA receiver with fixed point arithmetic

Bit-error rate performance of a two-user CDMA receiver with ...

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IEEE Conference on Vehicular Technology (VTC)

作者： Zhenlan Cheng M. Pesce D. Dahlhaus Communication Technology Laboratory Swiss Federal Institute of Technology Zurich Switzerland

fixed point arithmetic (FIPA) effects on the bit-error rate (BER) of a joint demodulation scheme for the uplink of a mobile radio system with direct sequence code-division multiple access are investigated. Results from Monte-Carlo simulations indicate that the robustness of the scheme against multiple-access interference being achieved for floating-point arithmetic operation can be preserved for FIPA at the expense of an increased BER for low interference levels. For a given word length in the FIPA operation, a threshold effect in the BER is observed if overflow is not suppressed. The threshold depends on the relative interference level and the adopted overflow handling. In moderate near-far scenarios, the performance can be improved by reducing the total dynamic range and increasing the accuracy of the decision variable of the weak signal.

关键词： Bit error rate Multiaccess communication Multiple access interference Receivers fixed-point arithmetic Demodulation Land mobile radio Robustness Floating-point arithmetic Dynamic range

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The influence of quantization and fixed point arithmetic upon the BER performance of turbo codes

The influence of quantization and fixed point arithmetic upo...

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IEEE Conference on Vehicular Technology (VTC)

作者： Yufei Wu B.D. Woerner Mobile and Portable Radio Research Group Virginia Polytechnic Institute and State University Blacksburg VA USA

The majority of the performance studies of turbo codes presented in the literature to date have assumed the use of floating point arithmetic. However, if fixed point arithmetic is employed, a corresponding degradation in the BER performance of the turbo decoding algorithm is expected. In this paper, the effects of quantization and fixed point arithmetic upon the log-MAP and APRI-SOVA decoding algorithms for a BPSK communication system are quantified via simulation. It is shown that, with proper scaling of the signal prior to quantization, no degradation of the BER performance is incurred with eight-bit quantization, and even four-bit quantization can provide acceptable BER performance.

关键词： Quantization fixed-point arithmetic Bit error rate Turbo codes Decoding Binary phase shift keying AWGN Floating-point arithmetic Degradation Signal to noise ratio

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