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''Individually normalized'' least mean square algorithm suitable for fixed-point processing and its application to active noise control

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ELECTRONICS AND COMMUNICATIONS IN JAPAN PART III-FUNDAMENTAL ELECTRONIC SCIENCE 1996年第4期79卷 62-73页

作者： Fujii, K Ohga, J Member Fujitsu Laboratories Ltd. Kawasaki Japan 211

By the fixed-point processing, a cheap and fast processor can be obtained which is an effective approach in reducing the production cost. In the adaptive filter, where the coefficient correction which is calculated in each sampling period to be added to the filter coefficient, the adjustment of the filter coefficient is made impossible if the coefficient correction is less than the minimum value that can be represented by the fixed-point representation. In the normalized least mean square (NLMS) algorithm, the normalization using the norm is applied, which increases the probability that the coefficient correction is less than the minimum value. This problem is solved by extracting the coefficient correction as the ''difference between the impulse response of the unknown signal transmission system as the object of identification and its estimation.'' In the ''individually normalized'' least mean square (LMS) algorithm, this difference is derived by calculating the ratio between the product-sum of the residual response with the adaptive filter output and the square-sum of the tap output. Then, the result is normalized individually for each coefficient. This paper then presents the stability condition which serves as the design principle of the proposed method. The parallel-shifting integrating configuration is presented, which has the computational complexity less than that of the NLMS algorithm. The method is applied to the filtered-x algorithm, and the usefulness is verified.

关键词： fixed-point processing coefficient correction individual normalization LMS algorithm

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Designing multi-dimensional logistic map with fixed-point finite precision

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NONLINEAR DYNAMICS 2019年第4期97卷 2147-2158页

作者： Munir, Fahad A. Zia, Muhammad Mahmood, Hasan Quaid I Azam Univ Dept Elect Islamabad Pakistan

In cryptographic algorithms, random sequences of longer period and higher nonlinearity are always desirable in order to increase resistance against cryptanalysis. The use of chaotic maps is an attractive choice as they exhibit properties that are suitable for cryptography. In continuous phase space of the logistic map, proper control parameters and initial state result into aperiodic trajectories. However, when the phase space of the logistic map is quantized, the trajectories terminate in finite and stable periodic orbits due to quantization error. The dynamic degradation of the logistic map can be mitigated using nonlinear feedback and cascading multiple chaotic maps. We propose a logistic map-based, finite precision multi-dimensional logistic map, that incorporates nonlinear feedback and modulus operations to perturb the chaotic trajectories. We present complexity, average cycle length and randomness analysis to evaluate the proposed method. The simulation results and analysis reveal that the proposed MDLM approach achieves longer period and higher randomness.

关键词： Digital chaotic map Multi-dimensional logistic map Finite precision Chaotic maps fixed-point processing

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A Parallel Systematic Resampling Algorithm for High-Speed Particle Filters in Embedded Systems

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CIRCUITS SYSTEMS AND SIGNAL processing 2014年第11期33卷 3591-3602页

作者： Gan, Qifeng Langlois, J. M. Pierre Savaria, Yvon Polytech Montreal Dept Comp & Software Engn Montreal PQ Canada Polytech Montreal Dept Elect Engn Montreal PQ Canada

In this paper, we propose a parallel systematic resampling (PSR) algorithm for particle filters, which is a new form of systematic resampling (SR). The PSR algorithm makes iterations independent, thus allowing the resampling algorithm to perform loop iterations in parallel. A fixed-point version of the PSR algorithm is also proposed, with a modification to ensure that a correct number of particles is generated. Experiments show that the fixed-point implementation of the PSR algorithm can use as few as 22 bits for representing the weights, when processing 512 particles, while achieving results equivalent to a floating-point SR implementation. Four customized instructions were designed to accelerate the proposed PSR algorithm in Application-Specific Instruction-set Processors. These four custom instructions, when configured to support four weight inputs in parallel, lead to a 73.7 speedup over a floating-point SR implementation on a general-purpose processor at a cost of 47.3 K additional gates.

关键词： Resampling algorithm Systematic resampling Particle Filters fixed-point processing Application-specific instruction-set processors (ASIPs)

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High-throughput scalable parallel resampling mechanism for effective redistribution of particles

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IEEE TRANSACTIONS ON SIGNAL processing 2006年第3期54卷 1144-1155页

作者： Hong, SJ Djuric, PM SUNY Stony Brook Dept Elect & Comp Engn Stony Brook NY 11794 USA

A novel resampling mechanism for parallel processing of fixed-point particle filtering is discussed. The proposed mechanism utilizes a particle-tagging scheme during quantization to compensate possible loss of replicated particles due to the finite precision effect. Particle tagging divides replicated particles into two groups for systematic redistribution of particles to eliminate particle localization in parallel processing. The mechanism utilizes an efficient interconnect topology for guaranteeing complete redistribution of particles even in case of potential weight unbalance among processing elements. The proposed architecture supports high throughput and ensures that the overall parallel particle filtering execution time scales with the number of processing elements employed.

关键词： fixed-point processing parallel resampling particle filters residual resampling scalable architecture

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Fast multiplication-free QWDCT for DV coding standard

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IEEE TRANSACTIONS ON CONSUMER ELECTRONICS 2004年第1期50卷 180-187页

作者： Silva, A Gouveia, P Navarro, A Univ Aveiro Inst Telecommun P-3810 Aveiro Portugal

This paper deals with fast computation of some operations included in the digital video (DV) coding standard. The proposed solution converts floating-point arithmetic operations into integer arithmetic operations;replacing highly computational demanding blocks such as discrete cosine transform (DCT), weighting (W) and quantization (Q) by fast integer calculations using only shifts and additions. The overall computational complexity was reduced by 73% in comparison to a floating-point implementation. Our solution is suitable to be programmed into any fixed-point arithmetic processor decreasing the consumer equipment cost. This solution is still compatible with the standard in terms of the DCT precision requirements(1).

关键词： digital video discrete cosine transform fixed-point processing quantization

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An efficient fixed-point implementation of residual resampling scheme for high-speed particle filters

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IEEE SIGNAL processing LETTERS 2004年第5期11卷 482-485页

作者： Hong, SJ Bolic, M Djuric, PM SUNY Stony Brook Dept Elect & Comp Engn Stony Brook NY 11794 USA

A novel low-complexity residual resampling scheme for particle filters is presented. The proposed scheme uses a simple but effective "particle-tagging" method to compensate for a possible error that can be caused by finite-precision quantization in the resampling step of particle filtering. The scheme guarantees that the number of particles after resampling is always equal to the number of particles before resampling. The resulting scheme is suitable for high-speed physical realization when the number of particles is a power of two.

关键词： fixed-point processing particle filters resampling residual resampling

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Fast IDCT implementation on hardware accelerator devices

Fast IDCT implementation on hardware accelerator devices

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IEEE International Symposium on Consumer Electronics

作者： Silva, A Nunes, O Aragao, C Navarro, A Univ Aveiro Inst Telecommun Dept Elect & Telecommun P-3810 Aveiro Portugal

ISBN: (纸本)0780385268

Most of hybrid motion compensated video coding standards use a well known discrete cosine transform (DCT) at the encoder to remove redundancy from video random processes. An inverse operation takes place at the decoder. As all calculations are done in floating point, some carefully design is needed when calculations are implemented in fixed point circuits. This paper proposes a high performance IDCT algorithm and its implementation using a FPGA. IDCT is one of the most computation-intensive parts of the video coding process. For this reason, a fast hardware. based IDCT implementation is crucial to speed-lip video processing.(1).

关键词： IDCT fixed-point processing hardware accelerators FPGA

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