In advanced power electronic applications such as a grid-tied solar photovoltaic (PV) inverter, control algorithms demand high-level computational support, typically provided by an expensive 32-bit digital-signal-proc...
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In advanced power electronic applications such as a grid-tied solar photovoltaic (PV) inverter, control algorithms demand high-level computational support, typically provided by an expensive 32-bit digital-signal-processor (DSP) or microcontroller. In cost-sensitive markets, this may prove to be a significant component of the overall cost of the system. Using a low-cost 16-bit microcontroller is, therefore, highly desirable. However, it poses certain challenges such as fewer bits for the mathematical and logical operations, computations in the fixed-point environment, and lower speeds. In this article, a novel per-unit integer system is proposed towards using a low-cost microcontroller for complex computations, which overcomes the above limitations while maintaining the core functionality in a fixed-point environment. An improved hybrid phase locked loop implementation scheme, that uses the p.u. integer system has also been presented, which significantly reduces the execution time for grid-synchronization. To demonstrate the performance of the proposed concepts, control of a grid-tied PV inverter has been implemented on a low-cost fixed-point microcontroller (dsPIC33FJ16GS402) as well as on an advanced DSP microcontroller (TMS320F28069). Timing analysis and experimental results for a 1 kW grid-tied PV system confirm that the performance of the system using a low-cost microcontroller is comparable to that of the advanced microcontroller.
This article presents the hardware implementation of the floating-point processor (FPP) to develop the radial basis function (RBF) neural network for the general purpose of pattern recognition and nonlinear control. T...
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This article presents the hardware implementation of the floating-point processor (FPP) to develop the radial basis function (RBF) neural network for the general purpose of pattern recognition and nonlinear control. The floating-point processor is designed on a field programmable gate array (FPGA) chip to execute nonlinear functions required in the parallel calculation of the back-propagation algorithm. Internal weights of the RBF network are updated by the online learning back-propagation algorithm. The on-line learning process of the RBF chip is compared numerically with the results of the RBF neural network learning process written in the MATLAB program. The performance of the designed RBF neural chip is tested for the real-time pattern classification of the XOR logic. Performances are evaluated by comparing results from the MATLAB through extensive experimental studies. (C) 2014 Elsevier By. All rights reserved.
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