A method for reducing hardware expenses in compositional microprogram control unit and CPLD chips is proposed. This method is based on the use of pseudoequivalent operational linear chains, wide fan-in of PAL macrocel...
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A method for reducing hardware expenses in compositional microprogram control unit and CPLD chips is proposed. This method is based on the use of pseudoequivalent operational linear chains, wide fan-in of PAL macrocells, and existence of free outputs of embedded memory block in CPLD chips. An example of applying the method is given. It is shown that the method reduces hardware expenses to 30%.
The method of design of compositional microprogram control unit with code sharing is proposed. The proposed method is based on application of special address transformer to form an address of microinstruction on the b...
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The method of design of compositional microprogram control unit with code sharing is proposed. The proposed method is based on application of special address transformer to form an address of microinstruction on the base of its representation as pair . Such approach permits to use all positive features of code sharing independently on characteristics of interpreted flowchart of algorithm, the optimal encoding of pseudoequivalent operational linear chains in particular. The proposed method permits to decrease the size of control memory in comparison with all known methods of such control units design. An example of proposed method application is given.
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