Several debugging methods are available for fpga design, including logical simulation and physical debug. We face the challenge to systematize and apply a simple methodology using these methods to develop a communicat...
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ISBN:
(纸本)9781538604151
Several debugging methods are available for fpga design, including logical simulation and physical debug. We face the challenge to systematize and apply a simple methodology using these methods to develop a communication processing module for a distributed control system with real time constraints. This methodology must follow some restrictions as to be easy to learn, use only available tools and not conflict with techniques employed by our industrial partner. The hardware module must be designed from scratch and must replace commercial communication modules in new devices. It will be responsible for real time interactions between programmable controllers and remote IO in large distributed control systems. The paper describes our experience designing the processing module, the methodology applied and an evaluation of this methodology during the project development.
fpgas have become indispensible in processor design, bring-up and debug. Traditionally fpgas have been used in prototyping, allowing end-users to emulate functionality of a specific component of a processor. However, ...
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ISBN:
(纸本)9781450311557
fpgas have become indispensible in processor design, bring-up and debug. Traditionally fpgas have been used in prototyping, allowing end-users to emulate functionality of a specific component of a processor. However, as the complexity of processors grows, another aspect of processor design, RTL verification, has become a prime target for acceleration using fpgas. Software-only RTL simulation and verification tools are no longer sufficient for many verification tasks as they often incur long execution time penalties. Software simulation time for a basic Linux kernel bring-up on a BlueGene/Q [1] processor, with 16 user PowerPC A2 cores, for example, could easily exceed several *** important feature of RTL verification acceleration using fpgas is its fast debugging capabilities. The ability to quickly and accurately pinpoint the location of an anomaly in an RTL source is highly desirable. This paper proposes efficient in-system debugging techniques on fpgas for RTL verification. We show how a network of over 45 Virtex 5 LX330 fpgas can be efficiently used to read out state information of the BlueGene/Q processor. We also demonstrate how the new in-system debugging technique is 250x faster than comparable methods.
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