检索结果-内蒙古大学图书馆

IEEE International Symposium on Circuits and Systems (IEEE ISCAS)

作者： Shi, Yongquan Sun, Yongshuai Jiang, Jianfei He, Guanghui Wang, Qin Jing, Naifeng Shanghai Jiao Tong Univ Dept Micro Nano Elect Shanghai Peoples R China

ISBN: (纸本)9781728192017

Resistive-RAM (ReRAM) based deep neural network (DNN) accelerator has shown great potential to address the memory wall problem for its processing-in-memory (PIM) capacity. However, ReRAM DNN accelerator still faces various challenges in its early architecture design phase due to the unpredictable variability and limitation of the ReRAM device. Software simulation helps but the simulation time is long with detailed ReRAM device model for large-scale DNNs. In this paper, we propose fast fpga-based emulation for the DNN accelerator of ReRAM device. The emulation sets a primitive DNN accelerator architecture in fpga and leverages fpga hardware resources to provide massive parallelism for reducing emulation time. Meanwhile, it is co-designed with runtime software stacks to make the hardware emulation more flexible via instruction compilation and scheduling for different DNN needs. Our experiments show that the emulation can get over 194.7X speedup for large-scale DNNs against NeuroSim as a software simulator for ReRAM DNN accelerator. Therefore, the proposed emulation helps to build better ReRAM accelerators for large DNNs with much higher speed and flexibility.

关键词： ReRAM PIM accelerator DNN fpga-based emulation

来源：评论

学校读者我要写书评

暂无评论

FITVS: A fpga-based emulation Tool For High-Efficiency Hardness Evaluation

FITVS: A FPGA-based Emulation Tool For High-Efficiency Hardn...

引用

IEEE International Symposium on Parallel and Distributed Processing with Applications

作者： Zheng, Hongchao Fan, Long Yue, Suge Beijing Microelect Technol Inst Beijing Peoples R China

ISBN: (纸本)9780769534718

This paper presents an improved tool called FITVS( Fault Injection Tool for Validating SEE) using the fpga-based emulation system for fault grading. A novel library-replace-modeling technique that can quickly and easily perform SEE by injecting faults into the circuit nodes is proposed It helps IC designers to enhance the quality of their design by providing the sensitivity information of all nodes. Also the fault injection effectiveness is improved with relative to the traditional methods by utilizing C# program and fpga emulation, and the speed of injection can reach the order of Ius/fault.

关键词： fpga-based emulation Fault Injection Fault/Error Models SEE simulating Injections Integrated circuits Ganglia Soundness

来源：评论

学校读者我要写书评

暂无评论

DEEP: An Iterative fpga-based Many-Core emulation System for Chip Verification and Architecture Research 11

DEEP: An Iterative FPGA-based Many-Core Emulation System for...

引用

19th Annual ACM International Symposium on Field-Programmable Gate Arrays

作者： Ributzka, Juergen Hayashi, Yuhei Gao, Guang R. Chen, Fei Univ Delaware Newark DE 19716 USA

ISBN: (纸本)9781450305549

This paper introduces the Delaware Enhanced emulation Platform (DEEP) - a fpga-based emulation system for hardware/software co-verification of many-core chip architectures. This platform exhibits the following three characteristics: fast compilation of logic designs, debugging support, and affordability. It is based on a novel iterative emulation methodology for hardware design and verification. We also conducted a logic design and integration of a new architectural feature that provides Full/Empty bit fine-grain synchronization for the IBM Cyclops-64 many-core architecture and evaluated its performance against existing synchronization constructs.

关键词： fpga-based emulation many-core architecture fine-grain synchronization

来源：评论

学校读者我要写书评

暂无评论

A unified environment for fault injection at any design level based on emulation

引用

IEEE TRANSACTIONS ON NUCLEAR SCIENCE 2007年第4期54卷 946-950页

作者： Lopez-Ongil, C. Entrena, L. Garcia-Valderas, M. Portela, M. Aguirre, M. A. Tombs, J. Baena, V. Munoz, F. Univ Carlos III Madrid Dept Tecnol Elect Madrid 28911 Spain Univ Seville Dept Elect Engn E-41012 Seville Spain

Sensitivity of electronic circuits to radiation effects is an increasing concern in modern designs. As technology scales down, Single Event Upsets (SEUs) are made more frequent and probable, affecting not only space applications, but also applications at earth's surface, like automotive applications. Fault injection is a method widely used to evaluate the SEU sensitivity of digital circuits. Among the existing fault injection techniques, those based on fpga emulation have proven to be the fastest ones. In this paper a unified emulation environment which combines two fault injection techniques based on fpga emulation is proposed. The new emulation environment provides both, a high speed tool for quick fault detection, and a medium speed tool for in-depth analysis of SEUs propagation. The experiments presented here show that the two techniques can be successfully applied in a complementary manner.

关键词： fault injection fpga-based emulation reconfiguration SEU

来源：评论

学校读者我要写书评

暂无评论

A unified environment for fault injection at any design level based on emulation

A unified environment for fault injection at any design leve...

引用

9th European Workshop on Radiation and its Effects on Components and Systems

关键词： fault injection fpga-based emulation reconfiguration SEU

来源：评论

学校读者我要写书评

暂无评论

Static scheduling of multidomain circuits for fast functional verification

引用

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2002年第11期21卷 1253-1268页

作者： Kudlugi, M Tessier, R Mentor Graph Corp Mentor Emulat Div Waltham MA 02451 USA Univ Massachusetts Dept Elect & Comp Engn Amherst MA 01003 USA

With the advent of system-on-a-chip design, many application specific integrated circuits (ASICs) now require multiple design clocks that operate asynchronously to each other. This design characteristic presents a significant challenge when these ASIC designs are mapped to parallel verification hardware such as parallel cycle-based simulators and logic emulators. In general, these systems require all computation and communication to be synchronized to a global system clock. As a result, the undefined relationship between design clocks can make it difficult to determine hold times for synchronous storage elements and causality relationships along reconvergent communication paths. This paper presents new scheduling and synchronization techniques to support accurate mapping of designs with multiple asynchronous clocks to parallel verification hardware. Through Analysis, it is shown that this approach is scalable to an unlimited number of domains And, supports increasingly large design sizes. To prove the effectiveness of the authors' approach, developed algorithms have been integrated into the compilation system for a commercial multi-fpga logic emulation system. For three designs mapped to a logic emulator using this software environment, modeling fidelity is maintained and performance is enhanced versus previous manual mapping approaches. A theoretical analysis based on Rent's rule validates the scalability of the approach as device sizes increase.

关键词： asynchronous circuits fpga-based emulation functional verification static scheduling

来源：评论

学校读者我要写书评

暂无评论

A Novel Implementation Methodology for Error Correction Codes on a Neuromorphic Architecture

引用

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2023年第12期42卷 4706-4720页

作者： Hassan, Sahil Dattilo, Parker Akoglu, Ali Univ Arizona Dept Elect & Comp Engn Tucson AZ 85721 USA

The Internet of Things infrastructure connects a massive number of edge devices with an increasing demand for intelligent sensing and inferencing capability. Such data-sensitive functions necessitate energy-efficient and programmable implementations of error correction codes (ECCs) and decoders. The algorithmic flow of ECCs with concurrent accumulation and comparison types of operations are innately exploitable by neuromorphic architectures for energy-efficient execution-an area that is relatively unexplored outside of machine learning applications. For the first time, we propose a methodology to map the hard-decision class of decoder algorithms on a neuromorphic architecture. We present the implementation of the Gallager B (GaB) decoding algorithm on a TrueNorth-inspired architecture that is emulated on the Xilinx Zynq ZCU102 MPSoC. Over this reference implementation, we propose architectural modifications at the neuron block level that result in a reduction of energy consumption by 31% with a negligible increase in resource usage while achieving the same error correction performance.

关键词： Error correction fpga-based emulation Gallager B (GaB) neuromorphic computing

来源：评论

学校读者我要写书评

暂无评论

Selective protection analysis using a SEU emulator:: testing protocol and case study over the leon2 processor

引用

IEEE TRANSACTIONS ON NUCLEAR SCIENCE 2007年第4期54卷 951-956页

作者： Aguirre, M. A. Tombs, J. N. Munoz, F. Baena, V. Guzman, H. Napoles, J. Fernandez-Leon, A. Tortosa-Lopez, F. Merodio, D. Univ Seville Escuela Super Ingn E-41092 Seville Spain European Space Agcy Microelect Sec TEC EDM ESTEC NL-2200 AG Noordwijk Netherlands

VLSI circuits for space application must be protected by the insertion of massive redundancy. However, this increases silicon area and the production costs, therefore designers can often consider leaving some large, noncritical subcircuits unprotected. This paper presents how FT-UNSHADES, a nonintrusive tool for fault injection on emulated hardware, helps designers to select the proper level of protection in every subeircuit. Using FT-UNSHADES, a test procedure is proposed that provides: 1) information about the quality of the test vectors, 2) a proper estimation of the number of injected faults required to get confidence about the results of a fault injection campaign, and 3) information about the criticality of individual subcircuits by selective fault injection campaigns. In addition, FT-UNSHADES allows the insertion of multi-bit flips. This test procedure has been applied to three different, protected and unprotected, versions of the well-known Leon2 processor, and the results are discussed here.

关键词： fault injection single event upset (SEU) fpga-based emulation fpga reconfiguration multi-bit upset ASIC

来源：评论

学校读者我要写书评

暂无评论

A Practical fpga-based Framework for Novel CMP Research 07

A Practical FPGA-based Framework for Novel CMP Research

引用

15th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

作者： Wee, Sewook Casper, Jared Njoroge, Njuguna Tesylar, Yuriy Ge, Daxia Kozyrakis, Christos Olukotun, Kunle Stanford Univ Comp Syst Lab Stanford CA 94305 USA

ISBN: (纸本)9781595936004

Chip-multiprocessors are quickly gaining momentum in all segments of computing. However, the practical success of CMPs strongly depends on addressing the difficulty of multithreaded application development. To address this challenge, it is necessary to co-develop new CMP architecture with novel programming models. Currently, architecture research relies on software simulators which are too slow to facilitate interesting experiments with CMP software without using small datasets or significantly reducing the level of detail in the simulated models. An alternative to simulation is to exploit the rich capabilities of modern fpgas to create fpga-based platforms for novel CMP research. This paper presents ATLAS, the first prototype for CMPs with hardware support for Transactional Memory (TM), a technology timing to simplify parallel programming. ATLAS uses the BEE2 multi-fpga board to provide a system with 8 PowerPC cores that, run at 100MHz and runs Linux. ATLAS provides significant benefits for CMP research such as 100x performance improvement over a software simulator and good visibility that helps with software tuning arid architectural improvements. Tit addition to presenting and evaluating ATLAS, we share our observations about building a fpga-based framework for CMP research. Specifically, we address issues such as overall performance, challenges of mapping ASIC-style CMP RTL on to fpgas, software support, the selection criteria for the base processor, and the challenges of using pre-designed IP libraries.

关键词： Chip Multi-processor Transactional Memory fpga-based emulation

来源：评论

学校读者我要写书评

暂无评论

Selective protection analysis using a SEU emulator:: testing protocol and case study over the leon2 processor

Selective protection analysis using a SEU emulator:: testing...

引用

9th European Workshop on Radiation and its Effects on Components and Systems

关键词： fault injection single event upset (SEU) fpga-based emulation fpga reconfiguration multi-bit upset ASIC

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：