In this paper, we propose a TC clustering method that simultaneously considers two data groups: the I/O workload and the function coverage for a higher level of firmware testing. Subsequently, we introduce an applicat...
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ISBN:
(纸本)9781665467063
In this paper, we propose a TC clustering method that simultaneously considers two data groups: the I/O workload and the function coverage for a higher level of firmware testing. Subsequently, we introduce an application model that predicts the function coverage using only the I/O workload of the TCs from the above method.
Fuzzing and symbolic execution are popular techniques for finding vulnerabilities and generating test-cases for programs. Fuzzing, a blackbox method that mutates seed input values, is generally incapable of generating...
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ISBN:
(纸本)9781450351911
Fuzzing and symbolic execution are popular techniques for finding vulnerabilities and generating test-cases for programs. Fuzzing, a blackbox method that mutates seed input values, is generally incapable of generating diverse inputs that exercise all paths in the program. Due to the path-explosion problem and dependence on SMT solvers, symbolic execution may also not achieve high path coverage. A hybrid technique involving fuzzing and symbolic execution may achieve better function coverage than fuzzing or symbolic execution alone. In this paper, we present Munch, an open-source framework implementing two hybrid techniques based on fuzzing and symbolic execution. We empirically show using nine large open-source programs that overall, Munch achieves higher (indepth) function coverage than symbolic execution or fuzzing alone. Using metrics based on total analyses time and number of queries issued to the SMT solver, we also show that Munch is more efficient at achieving better function coverage.
More than eighty different test environments need to be created and maintained for debugging the Marvell Ethernet PHY chip if the traditional industrial verification methodology is being used. This can easily incite v...
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ISBN:
(纸本)9781538635063
More than eighty different test environments need to be created and maintained for debugging the Marvell Ethernet PHY chip if the traditional industrial verification methodology is being used. This can easily incite very complicated debugging procedures and cause the problems and concerns of a multitude of engineering resources. The latest Marvell Ethernet PHY IC UVM verification platform integrating with the Marvell selected IP vendor's UVM library has been developed. A unique centralized-management methology block/architecture idea is brought in to build this UVM verification platform for the latest Marvell Ethernet PHY integrated circuit. All the eighty different test modes can be tested and verified in the same single UVM platform environment. This UVM verification platform environment significantly reduces the number of engineering resources needed to create and maintain the test cases. It also greatly saves debugging time and reduces chip development time. In the meanwhile, a novel random input stimulus controlled variables table idea is also implemented in this UVM verification platform to manage and improve the function coverage much more easily and efficiently.
This paper developed an advanced function coverage-directed reusable ASIC verification environment with automatic verification vectors generation. A layered architecture is adopted for reusing;the verification vectors...
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ISBN:
(纸本)9781424411313
This paper developed an advanced function coverage-directed reusable ASIC verification environment with automatic verification vectors generation. A layered architecture is adopted for reusing;the verification vectors are randomly generated and the simulation results can be checked automatically. Further more, Genetic algorithm is employed to improve the efficiency of the verification vectors generation. The result of experiments performed on a smart card showed this method to be effective and efficient.
This paper developed an advanced function coverage-directed reusable ASIC verification environment with automatic verification vectors generation. A layered architecture is adopted for reusing;the verification vectors...
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This paper developed an advanced function coverage-directed reusable ASIC verification environment with automatic verification vectors generation. A layered architecture is adopted for reusing;the verification vectors are randomly generated and the simulation results can be checked automatically. Further more, Genetic algorithm is employed to improve the efficiency of the verification vectors generation. The result of experiments performed on a smart card showed this method to be effective and efficient.
This paper developed an advanced function coverage-directed reusable ASIC verification environment with automatic verification vectors generation.A layered architecture is adopted for reusing;the verification vectors ...
详细信息
This paper developed an advanced function coverage-directed reusable ASIC verification environment with automatic verification vectors generation.A layered architecture is adopted for reusing;the verification vectors are randomly generated and the simulation results can be checked *** more,Genetic algorithm is employed to improve the efficiency of the verification vectors *** result of experiments performed on a smart card showed this method to be effective and efficient.
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