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functional coverage of the human genome by existing structures, structural genomics targets, and homology models

PLOS COMPUTATIONAL BIOLOGY 2005年第3期1卷 222-229页

作者： Xie, L Bourne, PE Univ Calif San Diego San Diego Supercomp Ctr San Diego CA 92103 USA Univ Calif San Diego Dept Pharmacol San Diego CA USA

The bias in protein structure and function space resulting from experimental limitations and targeting of particular functional classes of proteins by structural biologists has long been recognized, but never continuously quantified. Using the Enzyme Commission and the Gene Ontology classifications as a reference frame, and integrating structure data from the Protein Data Bank (PDB), target sequences from the structural genomics projects, structure homology derived from the SUPERFAMILY database, and genome annotations from Ensembl and NCBI, we provide a quantified view, both at the domain and whole-protein levels, of the current and projected coverage of protein structure and function space relative to the human genome. Protein structures currently provide at least one domain that covers 37% of the functional classes identified in the genome;whole structure coverage exists for 25% of the genome. If all the structural genomics targets were solved (twice the current number of structures in the PDB), it is estimated that structures of one domain would cover 69% of the functional classes identified and complete structure coverage would be 44%. Homology models from existing experimental structures extend the 37% coverage to 56% of the genome as single domains and 25% to 31% for complete structures. coverage from homology models is not evenly distributed by protein family, reflecting differing degrees of sequence and structure divergence within families. While these data provide coverage, conversely, they also systematically highlight functional classes of proteins for which structures should be determined. Current key functional families without structure representation are highlighted here;updated information on the "most wanted list" that should be solved is available on a weekly basis from http://***. org:8080/pdb/function-distribution/***..

关键词： .Human Genome Protein Data Bank Homology Ensembl functional classes functional coverage Structural Genomics Protein structures least one domain experimental structures single domains

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functional coverage - Driven UVM Based JTAG Verification 8

Functional Coverage - Driven UVM Based JTAG Verification

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8th IEEE International Conference on Computational Intelligence and Computing Research (IEEE ICCIC)

作者： Elakkiya, C. Murty, N. S. Babu, C. Jalan, Gaurav Amrita Univ Dept Elect & Commun Engn Bengaluru India Aricent Technol Holdings Bengaluru India

ISBN: (纸本)9781509066216

Traditional verification techniques using Verilog lack flexibility of reusable verification environment and faster time to market. The Universal Verification Methodology (UVM) Class Library provides the building blocks needed to develop reusable verification components and test environments using SystemVerilog. This paper focuses on developing a verification environment using SystemVerilog implementation of UVM for JTAG which will introduce an automated stimulus generating verification environment that checks the debugging functionality of JTAG for any given DUT. UVM based functional verification tries to achieve maximum functional coverage by adding constrained random test cases covering all possible scenarios. whereas, functional coverage model cannot be analyzed in traditional verification environment using Verilog. A functional coverage model is built here to find out whether the verification achieves the expected coverage or not. The coding is done using SystemVerilog and the simulation is done using Questasim

关键词： UVM JTAG Verification functional coverage

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functional coverage-Driven Characterization of RF Amplifiers

Functional Coverage-Driven Characterization of RF Amplifiers

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Forum on Specification and Design Languages (FDL)

作者： Hassan, Muhammad Grosse, Daniel Voertler, Thilo Einwich, Karsten Drechsler, Rolf DFKI GmbH Cyber Phys Syst D-28359 Bremen Germany Univ Bremen Inst Comp Sci D-28359 Bremen Germany COSEDA Technol GmbH Dresden Germany

ISBN: (纸本)9781728141138

In this paper we propose the first functional coverage-driven characterization approach as a systematic solution for the class of Radio Frequency (RF) amplifiers. We elevate the main concepts of digital functional coverage to the context of SystemC AMS in particular, and system-level simulations in general. To enable AMS functional coveragedriven characterization, we introduce two coverage refinement parameters on input and output side, to systematically generate input stimuli and capture specifications. At the heart of the approach is the coverage analysis which measures the functional coverage of the DUV and provides clear feedback to reach coverage closure. We provide a case study using an industrial RF transmitter and receiver model to demonstrate the applicability and efficacy of our approach.

关键词： SystemC AMS Virtual Prototyping functional coverage Analog/Mixed Signal RF Amplifiers

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Analyzing functional coverage in bounded model checking

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2008年第7期27卷 1305-1314页

作者： Grosse, Daniel Kuehne, Ulrich Drechsler, Rolf Univ Bremen D-28359 Bremen Germany

Formal verification is an important issue in circuit and system design. In this context, bounded model checking (BMC) is one of the most successful techniques. However, even if all the specified properties can be verified, it is difficult to determine whether they cover the complete functional behavior of a design. We propose a practical approach to analyze coverage in BMC. The approach can easily be integrated in a BMC tool with only minor changes. In our approach, a coverage property is generated for each important signal. If the considered properties do not describe the signal's entire behavior, the coverage property fails, and a counter example is generated. From the counter example, an uncovered scenario can be derived. This way, the approach also helps in design understanding. We demonstrate our method for a reduced instruction set computer (RISC) CPU. First, the coverage of the block-level verification is considered. Second, it is demonstrated how the technique can be applied on a higher level. Therefore, we investigate the instruction set verification of the RISC CPU. The experiments show that the costs for coverage analysis are comparable to the verification costs. Based on the results, we identified coverage gaps during the verification. We were able to close all of them and achieved 100% functional coverage in total.

关键词： Boolean satisfiability (SAT) bounded model checking (BMC) formal verification functional coverage

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Improving the functional coverage Closure of Network-on-Chip using Genetic Algorithm 56

Improving the Functional Coverage Closure of Network-on-Chip...

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56th IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Krishna, N. Vamshi Shah, Jay P. Soumya, J. BITS Pilani Hyderabad Campus Hyderabad India Invecas Technol Pvt Ltd Hyderabad India

ISBN: (纸本)9781665451093

Network-on-Chip (NoC) is a communication paradigm that has increased in popularity as a solution for intra-chip communication in complex System-on-Chip (SoC) designs, as it avoids complex interconnects. The functional verification of the NoC is a crucial step in the design life-cycle of a NoC based SoC, as it directly impacts the SoC behavior and latency. Automation of the NoC functional verification process could greatly improve the time-to-market of such complex SoC designs. One such approach to automation is the use of Genetic Algorithm to generate NoC traffic such that it achieves maximum functional coverage in less simulation time.

关键词： Network-on-Chip System-on-Chip Genetic Algorithm functional Verification functional coverage

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Architectural Trace-Based functional coverage for Multiprocessor Verification

Architectural Trace-Based Functional Coverage for Multiproce...

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13th International Workshop on Microprocessor Test and Verification (MTV)

作者： Mammo, Biruk Larimer, Jim Morgan, Matthew Fan, Dave Hennenhoefer, Eric Bertacco, Valeria Univ Michigan Ann Arbor MI 48109 USA ARM Ltd Cambridge England

ISBN: (纸本)9780769548777;9781467344418

functional coverage plays a pivotal role in assuring the quality of input stimuli used in the verification of modern digital designs. For an out-of-order multi-processor design, simulation of a detailed model of the design is often required to observe relevant design behaviors for functional coverage. However, since such a model is not available during the early phases of test development, verification teams are forced to wait until much later in the verification process to evaluate the quality of their test cases. Even then, the quality of the tests can be assured only on one specific design implementation - an undesirable characteristic for test and regression suites that are meant to be used across multiple generations and/or implementations of an architecture. This work addresses this issue by presenting a novel, implementation-independent, execution trace-based, coverage collection solution. Our solution enables the early evaluation of multi-processor tests using a high-level model of a design. In addition, it can be deployed with detailed design models, if desired, for further analysis alongside implementation-specific coverage models.

关键词： ARM functional coverage memory consistency multi-processor verification

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Improving functional coverage of Network-On-Chip Using Differential Evolution 18

Improving Functional Coverage of Network-On-Chip Using Diffe...

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18th International Conference on Ph.D Research in Microelectronics and Electronics (PRIME)

作者： Krishna, N. Vamshi Tripathy, Rahul Marripudi, Joshitha Soumya, J. BITS Pilani Dept EEE Hyderabad Campus Hyderabad 500078 Telangana India

ISBN: (纸本)9798350303209

Network-On-Chip (NoC) is a communication subsystem which has evolved as an alternative to bus-based System-On-Chip (SoC) architectures that simplify the physical implementation of the system. The functional verification of the NoC is a very important phase in the design life-cycle of a NoC-based SoC as it impacts the SoC's behavior and latency. Automating the NoC functional verification process significantly reduce the time to market for such complex SoC designs. The use of differential evolution algorithm to create NoC traffic which obtains maximum functional coverage in less simulation time is one such method of automation.

关键词： Network-on-Chip System-on-Chip Differential Evolution functional Verification functional coverage

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Evaluating Workloads Using Multi-comparative functional coverage

Evaluating Workloads Using Multi-comparative Functional Cove...

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5th International Haifa Verification Conference

作者： Adler, Yoram Ur, Shmuel Blue, Dale IBM Corp Haifa Res Lab Univ Campus IL-31905 Haifa Israel IBM Syst & Technol Grp Poughkeepsie NY 12601 USA

ISBN: (纸本)9783642192364

In this paper we present a technique for comparing multiple tests and workloads. We show how to automatically determine what each test does uniquely and how to present the information as succinctly as possible. This technology has a number of uses, including in understanding the contribution of tests in regression buckets, especially of legacy systems, and in evaluating what is missing in tests compared to customer usage. We also show that the technology used in the analysis is superior to previous technology in that it can automatically find holes that were previously only found manually.

关键词： functional coverage testing regression

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Achieving Last-Mile functional coverage in Testing Chip Design Software Implementations 23

Achieving Last-Mile Functional Coverage in Testing Chip Desi...

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IEEE/ACM 45th International Conference on Software Engineering - Software Engineering in Practice (ICSE-SEIP)

作者： Yan, Ming Chen, Junjie Mao, Hangyu Jiang, Jiajun Hao, Jianye Li, Xingjian Tian, Zhao Chen, Zhichao Li, Dong Xian, Zhangkong Guo, Yanwei Liu, Wulong Wang, Bin Sun, Yuefeng Cui, Yongshun Tianjin Univ Coll Intelligence & Comp Tianjin Peoples R China Huawei Noahs Ark Lab Beijing Peoples R China Huawei Hisilicon Beijing Peoples R China

ISBN: (纸本)9798350300376

Defective chips may cause huge losses (even disasters), and thus ensuring the reliability of chips is fundamentally important. To ensure the functional correctness of chips, adequate testing is essential on the chip design implementation (CDI), which is the software implementation of the chip under design in hardware description languages, before putting on fabrication. Over the years, while some techniques targeting CDI functional testing have been proposed, there are still a number of hard-to-cover functionality points due to huge input space and complex constraints among variables in a test input. We call the coverage of these points last-mile functional coverage. Here, we propose the first technique targeting the significant challenge of improving last-mile functional coverage in CDI functional testing, called LMT, which does not rely on domain knowledge and CDI internal information. LMT first identifies the relevant variables in test inputs to the coverage of last-mile functionality points inspired by the idea of feature selection in machine learning, so as to largely reduce the search space. It then incorporates Generative Adversarial Network (GAN) to learn to generate valid test inputs (that satisfy complex constraints among variables) with a larger possibility. We conducted a practical study on two industrial CDIs in Huawei to evaluate LMT. The results show that LMT achieves at least 49.27% and 75.09% higher last-mile functional coverage than the state-of-the-art CDI test input generation techniques under the same number of test inputs, and saves at least 94.24% and 84.45% testing time to achieve the same functional coverage.

关键词： Chip Design Testing Test Generation functional coverage Machine Learning

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Design and functional Verification of Axi2OCP Bridge for Highly Optimized Bus Utilization and Closure Using functional coverage 5th

Design and Functional Verification of Axi2OCP Bridge for Hig...

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5th International Conference on Frontiers in Intelligent Computing - Theory and Applications (FICTA)

作者： Shalini, N. Shashikala, K. P. Dayananda Sagar Coll Engn Bangalore Karnataka India

ISBN: (纸本)9789811031564;9789811031557

Given the density of current SOC's, Bridge design is used to connect interconnects working on different frequencies, protocols and bus widths. AXI and OCP are very commonly used protocols in industry given the fact that they support wide range of features. AXI2OCP bridge is used to connect 2 interconnects, one working on AXI protocol another on OCP protocol. Expected functioning of the Bridge design can be obtained by the process of verification, without proper verification the system may show unexpected behavior. Performance of the bus can be increased with effective bus utilization. Building verification environment for AXI2OCP Bridge using System verilog, Generating and simulating the test cases for various features of AXI and OCP, Measuring the Bus utilization parameter for the AXI 3.0 protocol, implementing functional coverage and assertions with the proposed integrated verification environment using Questa-sim tool is main idea of the paper.

关键词： AXI 3.0 protocol System Verilog functional coverage AXI2OCP bridge Bus utilization

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