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7th International Conference on Computing, Communications and Informatics (ICACCI)

作者： Vineeth, B. Sundari, B. Bala Tripura Amrita Vishwa Vidyapeetham Amrita Sch Engn Dept Elect & Commun Engn Coimbatore Tamil Nadu India

ISBN: (纸本)9781538653142

The scale and complexity of integrated circuit designs are ever expanding which makes the verification process increasingly difficult and progressively time consuming. This dictates the need for testbench architectures with generic verification components that are reusable and easily extendable across designs. The UVM can realize such testbench architectures with coverage driven verification environments useful for constrained random testing. This paper focus on the UVM based verification of SPI protocol according to the verification plan prepared after an exhaustive analysis of SPI functional specifications. The UVM testbench generates random vectors, drives the SPI module and compares the captured response with expected response using scoreboard mechanism to verify the SPI functionality. The testbench also validates the characteristic features of SPI by running appropriate test cases and reports coverage cumulatively at the end of each test. The simulation results are analyzed to evaluate the effectiveness of the proposed testbench.

关键词： Universal Verification Methodology functional Verification functional coverage Serial Peripheral Interface

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Design-intent coverage - A new paradigm for formal property verification

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2006年第10期25卷 1922-1934页

作者： Basu, Prasenjit Das, Sayantan Banerjee, Ansuman Dasgupta, Pallab Chakrabarti, Partha P. Mohan, Chunduri Rama Fix, Limor Armoni, Roy Indian Inst Technol Dept Comp Sci & Engn Kharagpur 721302 W Bengal India Intel Corp Folsom CA 95630 USA Intel Res Pittsburgh Pittsburgh PA 15213 USA Intel Corp IL-31015 Haifa Israel

It is essential to formally ascertain whether the register-transfer level (RTL) validation effort effectively guarantees the correctness with respect to the design's architectural intent. The design's architectural intent can be expressed in formal properties. However, due to the capacity limitations of formal verification, these architectural properties cannot be directly verified on the RTL. As a result, a set of lower level RTL properties are developed and verified against the RTL modules. In a top-down design approach, the architect would ideally like to formally guarantee the coverage of the architectural intent at the time of creating the specifications for the component RTL modules (that is, before they are passed to the designers for implementation). In this paper, the authors present: 1) a method for checking whether the RTL properties are covering the architectural properties, that is, whether verifying the RTL properties guarantees the correctness of the design's architectural intent;2) a method to identify which architectural properties are still uncovered, that is, not guaranteed by the RTL properties;and 3) a methodology for representing the gap between the specifications in a legible form.

关键词： formal verification functional coverage

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Accelerating assertion coverage with adaptive testbenches

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2008年第5期27卷 967-972页

作者： Pal, Bhaskar Banerjee, Ansuman Sinha, Arnab Dasgupta, Pallab Indian Inst Technol Dept Comp Sci & Engn Kharagpur 721302 W Bengal India

We present a new approach to bias random test generation for accelerating assertion coverage. The novelty of the proposed approach is that it treats the design under test as a black box and attempts to steer the simulation toward coverage points that are relevant for targeted assertions purely through external control. We present this approach over three different models with varying degrees of observability and control. The results demonstrate a significant speedup in assertion coverage as compared to randomized simulation.

关键词： design verification functional coverage test generation

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Fine-grained transaction-level verification: Using a variable transactor for improved coverage at the signal level

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2005年第8期24卷 1234-1240页

作者： Ara, K Suzuki, K Hitachi Ltd Cent Res Lab Tokyo 1858601 Japan

Maintaining coverage with increasing circuit scale has become a critical problem for logic-verification processes. While transaction-level verification (TLV) is an important step forward, fine-grained (FG) TLV provides better signal-level coverage by reactively changing transactors instead of transactionlevel scenarios. Evaluations with a microprocessor design show the effectiveness of FGTLV;all design bugs at the signal level were to be detected, though many were not detected by plain TLV.

关键词： functional coverage simulation transaction-level verification transactor

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Practical methods in coverage-Oriented verification of the Merom microprocessor

Practical methods in Coverage-Oriented verification of the M...

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43rd Design Automation Conference

作者： Gluska, Alon Intel MG MATAM Haifa Israel

ISBN: (纸本)1595933816

functional coverage is a well known means of measuring verification progress. However, approaches to coverage, such as coverage Driven and coverage Oriented approaches, are often difficult or impractical to implement. This paper presents the coverage methodology used in the verification of Merom, Intel's first converged-core microprocessor. We describe practical methods and applied techniques which enabled a high return on a significantly reduced investment in coverage measurement and analysis. Given the tight schedule, this approach provided a clear metric for measuring verification progress and for. effectively steering resources to improve the quality of the design under test.

关键词： logic design logic verification coverage functional coverage

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Enabling coverage-Based Verification in Chisel 27

Enabling Coverage-Based Verification in Chisel

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27th IEEE European Test Symposium (ETS)

作者： Dobis, Andrew Damsgaard, Hans Jakob Tolotto, Enrico Hesse, Kasper Petersen, Tjark Schoeberl, Martin Tech Univ Denmark Dept Appl Math & Comp Sci Lyngby Denmark

ISBN: (纸本)9781665467063

Ever-increasing performance demands are pushing hardware designers towards designing domain-specific accelerators. This has created a demand for improving the overall efficiency of the hardware design and verification cycles. The design efficiency was improved with the introduction of Chisel. However, verification efficiency has yet to be tackled. One method that can increase verification efficiency is the use of various types of coverage measures. In this paper, we present our opensource, coverage-related verification tools targeting digital designs described in Chisel. Specifically, we have created a new method allowing for statement coverage at an intermediate representation of Chisel, and several methods for gathering functional coverage directly on a Chisel description.

关键词： Hardware Verification Statement coverage functional coverage Chisel Scala

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coverage Evaluation of Post-silicon Validation Tests with Virtual Prototypes 14

Coverage Evaluation of Post-silicon Validation Tests with Vi...

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Design, Automation and Test in Europe Conference and Exhibition (DATE)

作者： Cong, Kai Lei, Li Yang, Zhenkun Xie, Fei Portland State Univ Dept Comp Sci Portland OR 97207 USA

ISBN: (纸本)9783981537024

High-quality tests for post-silicon validation should be ready before a silicon device becomes available in order to save time spent on preparing, debugging and fixing tests after the device is available. Test coverage is an important metric for evaluating the quality and readiness of post-silicon tests. We propose an online-capture offline-replay approach to coverage evaluation of post-silicon validation tests with virtual prototypes for estimating silicon device test coverage. We first capture necessary data from a concrete execution of the virtual prototype within a virtual platform under a given test, and then compute the test coverage by efficiently replaying this execution offline on the virtual prototype itself. Our approach provides early feedback on quality of post-silicon validation tests before silicon is ready. To ensure fidelity of early coverage evaluation, our approach have been further extended to support coverage evaluation and conformance checking in the post-silicon stage. We have applied our approach to evaluate a suite of common tests on virtual prototypes of five network adapters. Our approach was able to reliably estimate that this suite achieves high functional coverage on all five silicon devices.

关键词： elemental semiconductors quality control semiconductor device testing silicon concrete execution conformance checking coverage evaluation functional coverage high-quality tests network adapters online-capture offline-replay approach post-silicon stage post-silicon test quality post-silicon test readiness post-silicon validation tests silicon device test coverage virtual platform virtual prototype virtual prototypes Interface states Measurement Prototypes Registers Silicon Silicon devices Software

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Equivalence Checking Between SLM and TLM Using coverage Directed Simulation

Equivalence Checking Between SLM and TLM Using Coverage Dire...

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13th International Conference on Computer-Aided Design and Computer Graphics (CAD/Graphics)

作者： Hu, Jian Li, Tun Li, Sikun Natl Univ Def Technol Sch Comp Sci Changsha Hunan Peoples R China

ISBN: (纸本)9781479925766

The always increasing complexity of digital system makes designers start the design from more abstract System Level Modeling (SLM). However, the SLM arouses a new challenge for verification engineer to guarantee the functional equivalence between SLM specifications and Transaction Level Modeling (TLM) or other lower level implementations. This paper proposes a novel method for equivalence checking between SLM and TLM based on coverage directed simulation. In the proposed method, firstly quality measurements based on both code and functional coverage are used to generate simulation stimuli for SLM. Then the generated stimuli are used to simulate the SLM and TLM designs concurrently. Finally, equivalence checking is carried out based on the simulation results of the selected observing variables. With the proposed method, we can check the equivalence between SLM and TLM designs more efficiently with less simulation cost. The promising experimental results show the efficiency of our method.

关键词： System Level Modeling Transaction Level Modeling Equivalence Checking code coverage functional coverage

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A Verification Methodology for Reusable Test Cases and coverage Based on System Verilog

A Verification Methodology for Reusable Test Cases and Cover...

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2014 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)

作者： Chai, Lingling Xie, Zheng Wang, Xin'an Peking Univ Shenzhen Grad Sch Key Lab Integrated Microsyst Shenzhen 518055 Peoples R China

ISBN: (纸本)9781479923342

As the size and complexity of SoC design grow, it is common to establish a scalable and reusable verification test bench for verification engineers. To improve the efficiency of verification and reduce the development time and effort in chip design projects, the extensive and reusable test case model and function coverage model for the special circuit and the standard protocols should be focused on by verification engineers. In this paper, a verification methodology for reusable test cases and coverage is described. As an example, a reusable test bench of chain table DUT is utilized to verify the feasibility of the verification methodology.

关键词： Verification Methodology Reusability Test Case functional coverage

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coverage-oriented verification of banias 03

Coverage-oriented verification of banias

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40th Design Automation Conference

作者： Gluska, A Intel Israel Sci Ind Ctr IL-31015 Haifa Israel

ISBN: (纸本)1581136889

The growing complexity of state-of-art microprocessors dictates the use of cost-effective verification methods. functional coverage was widely applied in the verification of Banias, Intel's new IA-32 microprocessor designed solely for the mobile computing market. In this paper, we describe the practical coverage approach as Was carried out in the verification of Banias. According to this coverage-Oriented verification approach, focus shifts gradually from basic logic cleanup using. random testing, where verification follows a predefined test plan, to coverage-driven verification, where verification resources are steered to hit coverage holes. This practical approach enables reaching higher quality for lower effort under a tightened schedule, and provides a clear metric to measure the progress of verification and the. quality. of the design under test. As the conclusions will show, the retrospective evaluation of this approach shed light on its significant impact beyond original intentions, as well as uncovering several potential areas for refinement that will make this approach even more effective on future projects.

关键词： logic design logic verification coverage functional coverage

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