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7th International Workshop on Intelligent Solutions in Embedded Systems

作者： Vitullo, Francesco Saponara, Sergio Petri, Esa Casula, Michele Fanucci, Luca Maruccia, Giuseppe Locatelli, Riccardo Coppola, Marcello Univ Pisa Dept Informat Engn Pisa Italy STMicroectronics AST Grenoble Labs Grenoble France

ISBN: (纸本)9788887548013

functional verification plays an important role in the design now of an Intellectual Property (IP) core and, in general, of an embedded system. The industrial trend of the last two decades has been to produce more and more complex embedded systems by integrating several IP cores on a single chip die;while this is easily possible thanks to the availability of ready-to-use off-the-shelf components, the functional verification of the whole system becomes a major concern. Hand-written HDL testbenches or formal approaches to verification are no more feasible methods to assess good quality verification in a reasonable amount of time. To meet the new requirements of complex systems design, EDA companies are developing verification tools that bring rapid development, reusability concepts and automation techniques also in the world of functional verification. This work faces the issue of providing an automated verification environment for 2 Network-on-Chip component that is part of a complex communication infrastructure within a multi-core embedded system. In this context, reusability is a key feature of the environment, because it allows the user to easily move from component verification to network verification. The verification tool used in this work is Specman elite by Cadence and the IP it is applied to is a Spidergon-STNoC (by STMicroelectronics) component Verification environment design guidelines are provided together with a final coverage report summary.

关键词： Network-on-Chip (NoC) functional Verification functional coverage e Reuse Methodology (eRM) Intellectual Property (IP) Multi-Processor System-on-Chip (MPSoC)

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Using Machine Learning Clustering To Find Large coverage Holes 20

Using Machine Learning Clustering To Find Large Coverage Hol...

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2nd ACM/IEEE Workshop on Machine Learning for CAD (MLCAD)

作者： Gal, Raviv Simchoni, Giora Ziv, Avi IBM Res Haifa Haifa Israel

ISBN: (数字)9781450375191

ISBN: (纸本)9781450375191

Identifying large and important coverage holes is a time-consuming process that requires expertise in the design and its verification environment. This paper describes a novel machine learning-based technique for finding large coverage holes when the coverage events are individually defined. The technique is based on clustering the events according to their names and mapping the clusters into cross-products. Our proposed technique is being used in the verification of high-end servers. It has already improved the quality of coverage analysis and helped identify several environment problems.

关键词： functional coverage hole analysis clustering

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Optimized coverage-directed Random Simulation

Optimized Coverage-directed Random Simulation

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IEEE International High Level Design Validation and Test Workshop

作者： Ugarte, I. Sanchez, P. Univ Cantabria Microelect Engn Grp TEISA Dept ETSIIT E-39005 Santander Spain

ISBN: (纸本)9781424429226

Due to the growing complexity of modem digital systems, functional verification is still an important challenge. Current verification practice in industry and in academia includes simulation and formal techniques. While formal tools can handle small to medium size designs, only simulation-based tools can validate digital systems of almost infinite complexity. One of the main disadvantages of simulation is that only one set of behaviors is explored. In order to improve simulation, several coverage metrics have been proposed. These metrics (such as line, path or conditional coverage) provide information about the variety of behavior that a particular test-bench explores. With modern digital systems, it is difficult to obtain high coverage, thus a key challenge, according to the latest report of the ITRS, is to create new solutions that can provide high coverage at all hierarchical levels of a design. Verification plans commonly use random test bench generation. However, this technique normally provides a low coverage that is not improved by increasing the number of test-benches. The main contribution of this paper is the development of a behavioral verification technique that enables the improvement of the coverage of random test-benches, The algorithm takes advantage of the structure of the behavioral system description and the information that the simulation produces.

关键词： Semi-formal technique functional coverage random-based simulation solver

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coverage Metrics for Device Level Validation of SATA and SAS Devices - An Approach 5

Coverage Metrics for Device Level Validation of SATA and SAS...

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5th International Conference on Intelligent Systems, Modelling and Simulation (ISMS)

作者： Subramani, Raja Penneru, Ramya Selvaraj, Glamar Radhakrishnan, Bharath Puttaiah, Krishnamurthy Tech Mahindra Integrated Engn Serv Bombay Maharashtra India

ISBN: (纸本)9781479938575

This paper highlights the significance of coverage analysis with respect to the functionality and adherence to the standard specification of SATA, SAS, NVME & eMMC Devices (SSD's, HDD's). coverage analysis aims at achieving an effective way of testing the intrinsic functionality of the storage devices. Commands are issued to the Device under test to validate the attributes such as methods of transfer, latest technology involved to structure the storage device functionality, performance and the adherence to the protocol (SATA protocol). Validation environment of the storage device will include innumerable test cases which lead to redundancy of test scenarios and may cause gaps in the whole validation procedure rendering the goal to achieve a thorough validation output.

关键词： functional coverage Command coverage HDD SSD SATA SAS NVME eMMC coverage coverage Analysis

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How Good is Your Property? A New Metric for Formal Property coverage

How Good is Your Property? A New Metric for Formal Property ...

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2nd International Symposium of Electronics Design Automation (ISEDA)

作者： Zhao, Qianwen Zhang, Hongce Hong Kong Univ Sci & Technol Guangzhou Peoples R China

ISBN: (纸本)9798350352047;9798350352030

Formal property verification has been widely used in function verification, where user-specified properties are checked to ensure function correctness. However, as human verification engineers can also make mistakes when writing the properties, it is a general question on how to ensure the quality of formal properties. There are several existing coverage metrics, e.g., cone-of-influence (COI) and ProofCore coverage that assess the quality of properties in the setting of formal property verification. However, they are not sufficient to identify all coverage holes as this paper will show. Therefore, we propose FRcoverage, a new functional coverage metric for formal property verification, which is based on function reduction. Our case study shows that this new coverage metric successfully identifies three coverage holes in the commonly used RISCV-Formal verification framework when it is applied on PicoRV32 processor verification.

关键词： formal property verification functional coverage satisfiability modulo theories

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Faster coverage Closure: Runtime Guidance of Constrained Random Stimuli by Collected coverage

Faster Coverage Closure: Runtime Guidance of Constrained Ran...

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Saudi International Electronics, Communications and Photonics Conference (SIECPC)

作者： Yehia, Ahmed Mentor Graph Corp Cairo Egypt

ISBN: (纸本)9781467361958;9781467361965

Constrained Random Verification (CRV) provides a great value towards faster coverage closure over Directed Tests Verification. Yet, closing coverage is not an easy procedure given current designs' sizes and complexities. Long simulation runs, huge amount of random tests, directed tests covering specific corner cases, and others, are all techniques being used to close coverage. One of the reasons for challenges in closing coverage is redundant stimuli, stemming from the lack of a feedback from collected coverage to Constrained Random (CR) stimuli generators at run time (e. g. during simulation), which could result in missing interesting stimuli. This paper shows a standard and efficient way to avoid redundant stimuli by building a link between collected coverage and CR stimuli at run time seeking faster coverage closure, i.e. how collected coverage can dynamically guide random stimuli generators during simulation to generate uncovered scenarios, and avoid generating redundant ones.

关键词： functional Verification Constrained Random Verification Metric Driven Verification functional coverage

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Optimizing Constraint Selection in a Design Verification Environment for Efficient coverage Closure

Optimizing Constraint Selection in a Design Verification Env...

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作者： Cooper, Vanessa R. Nova Southeastern University

学位级别：Ph.D., Doctor of Philosophy

Hardware Design Verification, commonly called verification, is the process of functionally verifying a design that was written in a Register Transfer Language (RTL) based on the specification. The most common methodology in practice today uses the Universal Verification Methodology (UVM). In addition to being a methodology, UVM is also a collection of object-oriented base classes written in SystemVerilog. A UVM testbench is created that serves as a harness for the Design Under Test (DUT). Stimulus, with constrained random inputs, is written that exercises the design. Constrained Random Verification (CRV) is used to find functional errors in the design and to meet coverage goals. One form of coverage is functional coverage. functional coverage is defined and developed by the verification engineer to verify that certain scenarios are covered during simulation. coverage is created as a collection of coverpoints, and each coverpoint has one or more bins to indicate what is or is not hit. As a simple example, one coverpoint could be the write indicator for a First-In First-Out (FIFO) queue. This coverpoint would have two bins: one if the write indicator was high and another if it were low. For a large System-on-Chip (SOC) design, the number of bins to be covered could number in the tens of thousands. Reaching 100% coverage on such a design would require a large amount of compute space and potentially thousands of simulations running daily. The time it takes to analyze the coverage results and develop new stimulus to cover missing cases can take weeks to months, depending on the complexity of the design. To improve the efficiency and time it takes to reach coverage closure, this dissertation study evaluates the use of machine learning techniques. More specifically, this study uses a combination of Supervised Learning, Reinforcement Learning, and Bayesian Optimization to select constraints to reach coverage closure more efficiently. Using two different RTL models, the resu

关键词： Bayesian optimization Constrained random verification functional coverage IC design verification Machine learning Reinforcement learning

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A methodology aimed at better integration of functional verification and RTL design

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DESIGN AUTOMATION FOR EMBEDDED SYSTEMS 2005年第4期10卷 285-298页

作者： da Silva, Karina R. G. Melcher, Elmar U. K. Maia, Isaac Cunha, Henrique do N. Univ Fed Campina Grande Campina Grande PB Brazil

The advent of new 65 nm/90 nm VLSI technology and SoC design methodologies has brought an explosive growth in the complexity of modern electronic circuits. As a result, functional verification has become the major bottleneck in any digital design flow. Thus, new methods for easier, faster and more reusable verification are required. This paper proposes a verification methodology (VeriSC2) that guides the implementation of working testbenches during hierarchical decomposition and refinement of the design, even before the RTL implementation starts. This approach uses the SystemC Verification Library (SCV), in a tool capable of automatically generating testbench templates. A case study from a MPEG-4 decoder design is used to show the effectiveness of this approach.

关键词： functional verification functional coverage testbench VeriSC2 SystemC SCV

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On Error Injection for NoC Platforms: A UVM-Based Generic Verification Environment

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2020年第5期39卷 1137-1150页

作者： El-Ashry, Sameh Khamis, Mostafa Ibrahim, Hala Shalaby, Ahmed Abdelsalam, Mohamed El-Kharashi, M. Watheq Ain Shams Univ Dept Comp & Syst Engn Cairo 11517 Egypt Mentor Cairo 11361 Egypt Benha Univ Fac Comp & Informat Dept Comp Sci Banha 13518 Egypt Univ Victoria Dept Elect & Comp Engn Victoria BC V8P 5C2 Canada

Error injection has become critically important for testing the reliability of newly designed hardware systems. Evaluating how a design under test (DUT) reacts to different error-injection methodologies is essential for verification engineers to design dependable universal verification methodology (UVM) scoreboards for error-detection purposes. The first main contribution of this paper is to decide on the feasibility and compatibility of some error-injection techniques when used with networks-on-chip (NoC) platforms for simulation and hardware emulation environments. We target a UVM-based error-injection and detection environment with reusable components. Proposed techniques, introducing both positive and negative test scenarios, are applied to two examples of NoC components: 1) a base router and 2) Daniel router. Base router is a simple case study to prove proposed schemes, whereas Daniel router is a complex reconfigurable open-source case study. Daniel router provides the ability to change router architecture with some parameters and applied algorithms. The second main contribution of this paper is to integrate a full UVM environment with various verification approaches. Target approaches include error injection and detection using reusable and generic UVM environment and components for NoC. Network response is inspected according to error type and methodology. Finally, the proposed UVM environment is used to test and verify an ${N}\,\,{\times }\,\,{N}\,\,2$ -D network composed of base routers or Daniel routers.

关键词： Error injection functional coverage functional verification hardware emulation networks-on-chips (NoCs) universal verification methodology (UVM)

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Safe integration of parameterized IP

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INTEGRATION-THE VLSI JOURNAL 2004年第4期37卷 193-221页

作者： Jerinic, V Müller, D Tech Univ Chemnitz D-09107 Chemnitz Germany

In order to be reused in different applications Intellectual Properties (IP) are usually parameterized. On the one hand the extensive use of parameters enables users to customize IP to their needs in different applications. On the other hand a large number of parameters imposes new problems during IP qualification, verification and integration. This article gives an overview of the present work in the IP Qualification Project (IPQ) addressing problems due to IP parameterization. We are working on solutions to handle large parameter sets, to automatically implement parameter checking, and to improve functional coverage of the parameter space. Within this scope, a novel graph-based methodology to split the parameter space into orthogonal subspaces has been devised. On the basis of a formal description of parameters and their interdependences so-called Parameter Domain Graphs (PDG) are constructed. Relying on PDG, testbench components for assertion-based parameter checking are automatically generated. Furthermore, generation constraints for verification environments are derived and collection and analysis of functional coverage data is implemented. (C) 2004 Elsevier B.V. All rights reserved.

关键词： system-on-chip intellectual property design functional coverage verification parameter interdependences parameter domain graph

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