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International Conference on Intelligent Systems, Modelling and Simulation

作者： Raja Subramani Ramya Penneru Glamar Selvaraj Bharath Radhakrishnan Krishnamurthy Puttaiah Integrated Engineering Services Tech Mahindra

ISBN: (纸本)9781479938599

This paper highlights the significance of coverage analysis with respect to the functionality and adherence to the standard specification of SATA, SAS, NVME & eMMC Devices (SSD's, HDD's). coverage analysis aims at achieving an effective way of testing the intrinsic functionality of the storage devices. Commands are issued to the Device under test to validate the attributes such as methods of transfer, latest technology involved to structure the storage device functionality, performance and the adherence to the protocol (SATA protocol). Validation environment of the storage device will include innumerable test cases which lead to redundancy of test scenarios and may cause gaps in the whole validation procedure rendering the goal to achieve a thorough validation output.

关键词： functional coverage Command coverage HDD SSD SATA SAS NVME EMMC coverage coverage Analysis

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Equivalence Checking Between SLM and TLM Using coverage Directed Simulation

Equivalence Checking Between SLM and TLM Using Coverage Dire...

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13th International Conference on Computer-Aided Design and Computer Graphics (CAD/Graphics)

作者： Hu, Jian Li, Tun Li, Sikun Natl Univ Def Technol Sch Comp Sci Changsha Hunan Peoples R China

ISBN: (纸本)9781479925766

The always increasing complexity of digital system makes designers start the design from more abstract System Level Modeling (SLM). However, the SLM arouses a new challenge for verification engineer to guarantee the functional equivalence between SLM specifications and Transaction Level Modeling (TLM) or other lower level implementations. This paper proposes a novel method for equivalence checking between SLM and TLM based on coverage directed simulation. In the proposed method, firstly quality measurements based on both code and functional coverage are used to generate simulation stimuli for SLM. Then the generated stimuli are used to simulate the SLM and TLM designs concurrently. Finally, equivalence checking is carried out based on the simulation results of the selected observing variables. With the proposed method, we can check the equivalence between SLM and TLM designs more efficiently with less simulation cost. The promising experimental results show the efficiency of our method.

关键词： System Level Modeling Transaction Level Modeling Equivalence Checking code coverage functional coverage

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Faster coverage Closure: Runtime Guidance of Constrained Random Stimuli by Collected coverage

Faster Coverage Closure: Runtime Guidance of Constrained Ran...

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Saudi International Electronics, Communications and Photonics Conference (SIECPC)

作者： Yehia, Ahmed Mentor Graph Corp Cairo Egypt

ISBN: (纸本)9781467361958;9781467361965

Constrained Random Verification (CRV) provides a great value towards faster coverage closure over Directed Tests Verification. Yet, closing coverage is not an easy procedure given current designs' sizes and complexities. Long simulation runs, huge amount of random tests, directed tests covering specific corner cases, and others, are all techniques being used to close coverage. One of the reasons for challenges in closing coverage is redundant stimuli, stemming from the lack of a feedback from collected coverage to Constrained Random (CR) stimuli generators at run time (e. g. during simulation), which could result in missing interesting stimuli. This paper shows a standard and efficient way to avoid redundant stimuli by building a link between collected coverage and CR stimuli at run time seeking faster coverage closure, i.e. how collected coverage can dynamically guide random stimuli generators during simulation to generate uncovered scenarios, and avoid generating redundant ones.

关键词： functional Verification Constrained Random Verification Metric Driven Verification functional coverage

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An advanced Verification Environment based on VMM

An advanced Verification Environment based on VMM

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3rd International Conference on Advances in Materials Manufacturing (ICAMMP 2012)

作者： Wang, Jing Ji, Xinhua Yang, Ningxin Jia, Chao 39 572 LaneBibo Rd Shanghai Peoples R China

ISBN: (纸本)9783037856482

This paper presents an advanced verification environment based on VMM verification platform architecture which is constructed based on an object oriented language named System Verilog. The portable, reusable and extensible verification environment, which has a hierarchical structure, randomized excitation and self-check mechanism, efficiently improves the adequacy and reliability of verification and validation efficiency. The environment was used to verify an EEPROM controller which generated the reading and writing timing signals to operate EEPROM. The AHB bus function model-VIP, that used in the environment, reduced the development cycle efficiently. Additionally, the function coverage collected in the test platform gave an intuitive evidence of the verification adequacy and reliability.

关键词： VMM Verification Methodology Verification Platform VIP functional coverage

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Rapid functional MRI in the mouse heart at 11.7T

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Journal of Cardiovascular Magnetic Resonance 2013年第1期15卷 1-2页

作者： Subgang, A. Vernikouskaya, I. Rasche, V. CF-Small Animal MRI Ulm University Ulm Germany

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Analyzing functional coverage in bounded model checking

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2008年第7期27卷 1305-1314页

作者： Grosse, Daniel Kuehne, Ulrich Drechsler, Rolf Univ Bremen D-28359 Bremen Germany

Formal verification is an important issue in circuit and system design. In this context, bounded model checking (BMC) is one of the most successful techniques. However, even if all the specified properties can be verified, it is difficult to determine whether they cover the complete functional behavior of a design. We propose a practical approach to analyze coverage in BMC. The approach can easily be integrated in a BMC tool with only minor changes. In our approach, a coverage property is generated for each important signal. If the considered properties do not describe the signal's entire behavior, the coverage property fails, and a counter example is generated. From the counter example, an uncovered scenario can be derived. This way, the approach also helps in design understanding. We demonstrate our method for a reduced instruction set computer (RISC) CPU. First, the coverage of the block-level verification is considered. Second, it is demonstrated how the technique can be applied on a higher level. Therefore, we investigate the instruction set verification of the RISC CPU. The experiments show that the costs for coverage analysis are comparable to the verification costs. Based on the results, we identified coverage gaps during the verification. We were able to close all of them and achieved 100% functional coverage in total.

关键词： Boolean satisfiability (SAT) bounded model checking (BMC) formal verification functional coverage

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A functional Verification Methodology Based on Parameter Domains for Efficient Input Stimuli Generation and coverage Modeling

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JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS 2011年第4期27卷 485-503页

作者： Castro Marquez, Carlos Ivan Romero Tobar, Edgar Leonardo Strum, Marius Chau, Wang Jiang Univ Sao Paulo Sch Engn BR-05424970 Sao Paulo Brazil

Modern Integrated Circuit (IC) design is characterized by a strong trend of Intellectual Property (IP) core integration into complex system-on-chip (SOC) architectures. These cores require thorough verification of their functionality to avoid erroneous behavior in the final device. Formal verification methods are capable of detecting any design bug. However, due to state explosion, their use remains limited to small circuits. Alternatively, simulation-based verification can explore hardware descriptions of any size, although the corresponding stimulus generation, as well as functional coverage definition, must be carefully planned to guarantee its efficacy. In general, static input space optimization methodologies have shown better efficiency and results than, for instance, coverage Directed Verification (CDV) techniques, although they act on different facets of the monitored system and are not exclusive. This work presents a constrained-random simulation-based functional verification methodology where, on the basis of the Parameter Domains (PD) formalism, irrelevant and invalid test case scenarios are removed from the input space. To this purpose, a tool to automatically generate PD-based stimuli sources was developed. Additionally, we have developed a second tool to generate functional coverage models that fit exactly to the PD-based input space. Both the input stimuli and coverage model enhancements, resulted in a notable testbench efficiency increase, if compared to testbenches with traditional stimulation and coverage scenarios: 22% simulation time reduction when generating stimuli with our PD-based stimuli sources (still with a conventional coverage model), and 56% simulation time reduction when combining our stimuli sources with their corresponding, automatically generated, coverage models.

关键词： System-on-chip functional verification Random-constrained simulation functional coverage Parameter domains Testbench code automation

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Development of Verification Envioronment for SPI Master Interface Using SystemVerilog

Development of Verification Envioronment for SPI Master Inte...

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2012 IEEE 11th International Conference on Signal Processing(ICSP 2012)

作者： Zhili Zhou Zheng Xie Xin’an Wang Teng Wang Key Lab of Integrated Micro-Systems Peking University Shenzhen Graduate School

ISBN: (纸本)9781467321969

System-level verification with scalable and reusable components provides a solution for current complex SOC verification and SystemVerilog with OOP is one of the most promising language to develop a complete verification environment with constrained random testing, functional coverage and assertions. In this paper, a uniform verification environment for SPI master interface is developed using SystemVerilog after a comprehensive analysis of the verification plan. The proposed multi-layer testbench is comprised of APB driver, SPI slave, scoreboard, checker, coverage analysis and assertions, which are implemented with different properties of SystemVerilog. Furthermore, constrained random testing vectors are generated automatically and driven into the DUT for higher functional coverage. The verification result shows the effectiveness of the proposed verification environment, which is of great feasibility for further extension and reuse.

关键词： SystemVerilog object-oriented programming SPI interface functional coverage assertion

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A Verification Method of Multi-Threaded Processor Based on Tree-structure

A Verification Method of Multi-Threaded Processor Based on T...

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7th International Conference on MEMS, NANO and Smart Systems (ICMENS 2011)

作者： Ma, Peijun Liu, Meng Li, Kang Shi, Jiangyi Xidian Univ Sch Microelect Minist Educ Key Lab Wide Band Gap Semicond Mat & Devices Xian Shanxi Peoples R China

ISBN: (纸本)9783037853122

A method based on tree-structure for verifying a multi-threading processor is described in this paper. In this method, instructions are classified according to tree-structure, instruction stream is generated by hierarchical random and the tree-structure is pruned by feedback information of functional coverage model. Results show that this method can speed up the convergence of the coverage and supply effective functional verification for micro-engine.

关键词： Tree-Structure functional coverage Processor Verification

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functional Verification of Network Processor

Functional Verification of Network Processor

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IEEE International Conference on Electronics, Communications and Control (ICECC)

作者： Ma, Pei-Jun Jiang, Yong Li, Kang Shi, Jiang-Yi Xidian Univ Dept Microelect Xian Peoples R China

ISBN: (纸本)9781457703218

Network processor is a type of specific instruction set processor which is used to process the data packet and possess specific circuit. In this paper, based on the testbench of network processor, functional coverage models are built by the two types of functional coverage expression provided by SystemVerilog. The functional coverage can be obtained automatically by these models. According to the functional coverage, we can modify the testcases to get a fast convergence of functional coverage, so that the network processor acquires efficient functional verification. To reduce the time to fix bugs' position, the assertion of property is also discussed in the paper.

关键词： network processor testbench functional coverage covergroup property

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