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gate array Using Low-Temperature Poly-Si Thin-Film Transistors

IEICE TRANSACTIONS ON ELECTRONICS 2020年第7期E103C卷 341-344页

作者： Kimura, Mutsumi Inoue, Masashi Matsuda, Tokiyoshi Ryukoku Univ Dept Elect & Informat Otsu Shiga 5202194 Japan High Tech Res Ctr Innovat Mat & Proc Res Ctr Otsu Shiga 5202194 Japan

We have designed gate arrays using low-temperature poly-Si thin-film transistors and confirmed the correct operations. Various kinds of logic gates are beforehand prepared, contact holes are later bored, and mutual wiring is formed between the logic gates on demand. A half adder, two-bit decoder, and flip flop are composed as examples. The static behaviors are evaluated, and it is confirmed that the correct waveforms are output. The dynamic behaviors are also evaluated, and it is concluded that the dynamic behaviors of the gate array are less deteriorated than that of the independent circuit.

关键词： gate array low-temperature poly-Si (LTPS) thin-film transistor (TFT)

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Heat diffusion in an optical logic gate array on silicon-on-sapphire

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JOURNAL DE PHYSIQUE III 1997年第3期7卷 739-748页

作者： Gualous, H Koster, A Pascal, D Laval, S UNIV PARIS 11 INST ELECT FONDAMENTALECNRS URA 22F-91405 ORSAYFRANCE

Designing optical logic gate array needs to reduce thermal interactions between pixels. Heat diffusion between an active pixel and its neighbours is calculated using an original method derived from the electrostatic image method. Temperature variations are calculated as a function of the distance from the pixel center. The mean temperature rises of the various pixels are estimated and thermal influence between adjacent pixels is determined.

关键词： .pixels Heat diffusion Optical Logic gate array Silicon-on-Sapphire

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A secure dynamically programmable gate array based on ferroelectric memory

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FUJITSU SCIENTIFIC & TECHNICAL JOURNAL 2003年第1期39卷 52-61页

作者： Oura, M Masui, S Fujitsu Labs Ltd Nakahara Ku Kawasaki Kanagawa 211 Japan

The field programmable gate array (FPGA) market is expanding because FPGAs enable faster development times and lower development costs than mask programmable gate arrays (MPGAs).(1)) However, the conventional SRAM-based FPGA requires off-chip, non-volatile PROMs to store configuration data, which increases the total device cost and the board area. To provide a low-cost solution for field programmable devices, we have developed a non-volatile, 8-context, dynamically programmable gate array (DPGA(note))) using ferroelectric RAM (FeRAM) technology. The developed configuration memory, which consists of a SRAM-based 6-transistor/4-ferroelectric-capacitor cell, has an access time comparable to that of a standard SRAM. It also has a non-destructive read operation and a stable data recall scheme. In addition, the contents of the configuration memory are securely protected. We have fabricated a prototype DPGA that combines 0.35 mum CMOS and FeRAM technologies. Using this device, we have executed the Data Encryption Standard (DES) functions at up to 51 MHz at 3.3 V. We confirmed that the minimum non-volatile operating voltage is 1.5 V.

关键词： .consists non-destructive DPGA context field programmable configuration data SRAM-based configuration memory gate array FeRAM Secure Dynamically Programmable Based on Ferroelectric

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DESIGN OF THE BASIC CELL AND METALLIZED RAM FOR 0.5 MU-M CMOS gate array

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IEICE TRANSACTIONS ON ELECTRONICS 1995年第9期E78C卷 1255-1262页

作者： NISHIO, Y HARA, H IWAMURA, M KAMINAGA, Y KOIKE, K HIROSE, K NOTO, T OGUCHI, S YAMAMOTO, Y ONO, T Hitachi Ltd Hitachi-shi Japan

A 0.5 mu m CMOS embedded function type gate array family with high speed modules was developed. This family has: an effective basic cell;high speed, compiled type metallized and diffused RAMs;PLL (Phase Locked Loop);and GTL (Gunning Transceiver Logic) to realize operation of over 100 MHz at 3.3 V. This paper describes the basic cell architecture and the compiled type metallized RAM. A divided MOS transistor type basic cell is effective for metallized modules such as metallized RAM and internal logic circuits. The appropriate basic cell size (height) can be decided from the viewpoints of the relationship between the number of usable basic cells and the basic cell height, and the logic circuit speed. Propagation delay time of the 2-input NAND is 200 ps at a standard load of fan out=2 and metal length=1.4 mm. For the universal ASIC, the compiled RAM is indispensable. Single port and multi-port metallized RAMs which are structured by using the basic cells are discussed. The new single port memory cell circuit which has a differential write and single end read operating method is introduced. This memory cell circuit can be realized using one basic cell. The diffused layer region of the NMOS transfer gates for the read operation is shared between neighbor memory cells. So, the capacitance of the bit line becomes smaller, and a high speed access time can be achieved. The measured access time of 1 kbits is 4.2 ns. The new multi-port memory cell circuits which have a single end write and single end read operating method are introduced. The read operating method is the same as that of the single port memory cell circuit. The access time shows very high speed operation comparable to that of the single port memory. This 3F (Flexible, Fast, and Friendly) ASIC family can be applied to high speed processors in workstations and graphics equipment.

关键词： gate array BASIC CELL COMPILED RAM METALLIZED RAM

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A CAD-compatible SOI-CMOS gate array using 0.35 μm partially-depleted transistors

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IEICE TRANSACTIONS ON ELECTRONICS 2000年第2期E83C卷 205-211页

作者： Ueda, K Nii, K Wada, Y Maeda, S Iwamatsu, T Yamaguchi, Y Ipposhi, T Maegawa, S Mashiko, K Horiba, Y Mitsubishi Elect Corp Syst LSI Dev Ctr Itami Hyogo 6648641 Japan Mitsubishi Elect Corp ULSI Dev Ctr Itami Hyogo 6648641 Japan

This paper describes a 0.35 mu m SOI-CMOS gate array using partially-depleted transistors. The gate array adopts the field-shield isolation technique with body-tied structures to suppress floating-body problems such as: (1) kink characteristics in drain currents, (2) low break-down voltage, and (3) frequency-dependent delay time. By optimizing the basic-cell layout and power-line wiring, the SOI-CMOS gate array also allows the use of the cell libraries and the design methodologies compatible with bulk-CMOS gate arrays. An ATM (Asynchronous Transfer Mode) physical-layer processing LSI was fabricated using a 0.35 mu m SOI-CMOS gate array with 560k raw gates. The LSI operated at 156 Mbps at 2.0 V, while consuming 71% less power than using a typical 0.35 mu m 3.3 V bulk-CMOS gate array.

关键词： SOI CMOS field-shield isolation gate array low-power high-speed

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HIGH-SPEED DIVIDER USING GAAS ECL CML gate array

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ELECTRONICS LETTERS 1989年第7期25卷 432-433页

作者： TOPHAM, PJ PARTON, JG GOLDER, MJ HOLLIS, BH HIAMS, NA GOODFELLOW, RC COOK, MP PLESSEY SEMICOND LTD SWINDONWILTSENGLAND

An ECL/CML gate array using GaAs/AlGaAs heterojunction bipolar transistors is reported for the first time. The gate array has up to 12 programmable inputs and outputs. A divide-by-eight circuit configured on this arra... 详细信息

关键词： 3.1 GHz CML GaAs-AlGaAs HBT III-V semiconductors aluminium compounds bipolar integrated circuits clock frequency counting circuits counting circuits ECL divide-by-eight circuit dividers dividing circuits emitter-coupled logic gallium arsenide gate array heterojunction bipolar transistors heterojunction bipolar transistors integrated circuit technology logic arrays programmable inputs semiconductors

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SELECTION ASSISTANT SYSTEM FOR gate array USER

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ENGINEERING APPLICATIONS OF ARTIFICIAL INTELLIGENCE 1993年第6期6卷 519-531页

作者： CHOY, CS FUNG, CH CHAN, CF CHINESE UNIV HONG KONG DEPT ELECTR ENGNSHA TINHONG KONG

The problem of selecting the most suitable gate array for a design simply arises from the abundance of choices and the lack of commonly adopted and well defined criteria. This is a particularly difficult problem for an inexperienced gate array user. The selection assistant system described resorts to expert-system techniques to make the selection process transparent to a user. The system establishes user requirements either through interactive dialogue or automatic extraction from a schematic. Selection criteria are divided into electrical and technical aspects. Examples of the former are delay, gate count, etc., whereas those of the latter are computer facilities, price, etc. As the system is designed to be adaptive, the knowledge base can be modified and fine-tuned. It is suggested that the system should be tailored to a specific working environment in practical use.

关键词： gate array EXPERT SYSTEM ELECTRONIC DESIGN AUTOMATION

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TIC TAC TOE game using an optically routed gate array 6

TIC TAC TOE game using an optically routed gate array

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Current Developments in Optical Design and Engineering VI Conference

作者： Vogel, EP Pacific Communications Sciences Inc. (United States)

An optically routed gate array(OPGA) is used to implement a simple game of TIC TAC TOE to demonstrate the utility of electrooptical circuits which embody user input, display and logic functions in a single device. Pro... 详细信息

ISBN: (纸本)0819422517

关键词： electrooptic logic optical routing gate array neon photoconductor LED

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Radiation-hardened gate array with embedded SRAM 15

Radiation-hardened gate array with embedded SRAM

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2015 15th European Conference on Radiation and Its Effects on Components and Systems (RADECS)

作者： Malashevich, N. Makarceva, M. Fedorov, R. Sci Mfg Complex Technol Ctr Moscow Russia Natl Res Univ Elect Technol MIET Moscow Russia

the problem of information storage reliability improvement in random access memory (RAM) devices oriented to application as part of gate arrays designed for space-related application is considered in this article.

ISBN: (纸本)9781509002320

关键词： RAM memory cell gate array radiation hardness

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Formation of holographic memory for optically reconfigurable gate array by angle-multiplexing recording of multi-circuit information in liquid crystal composites

Formation of holographic memory for optically reconfigurable...

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Conference on Emerging Liquid Crystal Technologies IX

作者： Ogiwara, Akifumi Maekawa, Hikaru Watanabe, Minoru Moriwaki, Retsu Kobe City Coll Technol Dept Elect Engn Nishi Ku 8-3 Gakuen Higashi Kobe Hyogo 6512194 Japan Shizuoka Univ Fac Engn Dept Elect & Elect Engn Hamamatsu Shizuoka 4328561 Japan

ISBN: (纸本)9780819499172

A holographic polymer-dispersed liquid crystal (HPDLC) memory to record multi-context information for an optically reconfigurable gate array is formed by the angle-multiplexing recording using a successive laser exposure in liquid crystal (LC) composites. The laser illumination system is constructed using the half mirror and photomask written by the different configuration contexts placed on the motorized stages under the control of a personal computer. The fabricated holographic memory implements a precise reconstruction of configuration contexts corresponding to the various logical circuits such as OR circuit and NOR circuit by the laser illumination at different incident angle in the HPDLC memory.

关键词： holographic memory recording liquid crystal optically reconfiguration laser angle-multiplexing gate array multi-circuit

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