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17th Dallas Circuits and Systems Conference (DCAS)

作者： Kamali, Hadi Mardani Univ Cent Florida Dept Elect & Comp Engn ECE Orlando FL 32816 USA

ISBN: (纸本)9798350349535;9798350349542

The employment of fully reconfigurable logic and routing modules represents a promising and potentially resilient approach to combating intellectual property (IP) piracy and the overproduction of integrated circuits (IC). Over time, the utilization of such reconfigurable logic has evolved within the realm of hardware security, encompassing a spectrum of protective measures and security monitoring solutions. This evolution underscores a technological transition within this domain, shifting from full-custom ASICs to gate-array ASICs to enhance robustness. This paper delineates the progression within this field, tracing advancements from rudimentary look-up-table based methods to sophisticated partial reconfigurable ASICs featuring embedded FPGAs (eFPGAs). The investigation critically evaluates the merits and limitations of each technique, and advocates for a strategic trajectory that optimizes efficiency and upholds the promised robustness.

关键词： Hardware IP Piracy ASIC FPGA gate-array

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A 5-10 GHz SiGeBiCMOS FPGA with new configurable logic block

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MICROPROCESSORS AND MICROSYSTEMS 2005年第2-3期29卷 121-131页

作者： You, C Guo, JR Kraft, RP Chu, M Curran, P Zhou, K Goda, B McDonald, JF Rensselaer Polytech Inst Troy NY 12180 USA

This paper presents a new multiplexer based FPGA, which can operate at a clock frequency of 5-10 GHz. Redundant switches on the original signal paths are removed improving the performance. The configurable logic blocks (CLBs) power is greatly reduced by using a revised multiplexer structure and turning off unused cells dynamically. More routing capabilities are provided with more inputs/outputs in each direction than similar designs. A chip consisting of four FPGA ring oscillators was fabricated. The Spice simulation results and chip measurement, are presented, (C) 2004 Elsevier B.V. All rights reserved.

关键词： field programmable gate array gate-array high-performance low-power-design SiGe programmable logic array reconfigurable-system current mode logic

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Rent exponent prediction methods

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2000年第6期8卷 679-688页

作者： Christie, P Univ Delaware Dept Elect & Comp Engn Newark DE 19716 USA

A wide variety of models for estimating the distribution of on-chip net lengths assume an accurate estimate for an empirical parameter called the Rent exponent. Due to its definition as an exponent, these models are sensitive to its precise value, and careful selection is essential for good estimates of layout requirements and cycle times. in addition, it is also important to be able to predict changes in the Rent exponent with (possibly discontinuous) changes in interconnect technology. This paper presents a range of methods for estimating the Rent exponents of arbitrarily large gate placements as a function of optimization procedure and the level of fan-out present in the netlist. The first part of the paper describes a rapid algorithmic approach which combines the self-similar, or fractal, attributes of small wiring cells with a Monte Carlo sampling method. This method is shown to accurately account for variations in both the wiring signature of the netlist and for the effects of most algorithms used for placement optimization. The second part of the paper presents an analytical model for Rent exponent prediction, based on a renormalization group transformation. This transformation is designed to filter out information which does not contribute to the scale-invariant properties of the optimized netlist enabling the derivation of a closed-form expression for the Rent exponent.

关键词： analysis clustering critical-path gate-array partitioning Ulsi

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Speed and area tradeoffs in cluster-based FPGA architectures

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2000年第1期8卷 84-93页

作者： Marquardt, A Betz, V Rose, J Right Track CAD Corp Toronto ON M5S 2T9 Canada Univ Toronto Dept Elect & Comp Engn Toronto ON M5S 3G4 Canada

One way to reduce the delay and area of field-programmable gate arrays (FPGA's) is to employ logic-cluster-based architectures, where a logic cluster is a group of logic elements connected with high-speed local interconnections. In this paper, we empirically evaluate FPGA architectures with logic clusters ranging in size from 1 to 20, and show that compared to architectures with size 1 clusters, architectures with size 8 clusters have 23% less delay (30% faster clock speed) and require 14% less area. We also show that FPGA architectures with large cluster sizes can significantly reduce design compile time-an increasingly important concern as the logic capacity of FPGA's rises. For example, an architecture that uses size 20 clusters requires seven times less compile time than an architecture with size 1 clusters.

关键词： clustering design gate-array high-performance high-speed interconnect performance tradeoffs

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The interpretation and application of Rent's rule

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2000年第6期8卷 639-648页

作者： Christie, P Stroobandt, D Univ Delaware Dept Elect & Comp Engn Newark DE 19716 USA Univ Ghent ELIS Dept B-9000 Ghent Belgium

This paper provides a review of both Rent's rule and the placement models derived from it. It is proposed that the power-law form of Rent's rule, which predicts the number of terminals required by a group of gates for communication with the rest of the circuit, is a consequence of a statistically homogeneous circuit topology and gate placement, The term "homogeneous" is used to imply that quantities such as the average wire length per gate and the average number of terminals per gate are independent of the position within the circuit. Rent's rule is used to derive a variety of net length distribution models and the approach adopted in this paper is to factor the distribution function into the product of an occupancy probability distribution and a function which represents the number of valid net placement sites. This approach places diverse placement models under a common framework and allows the errors introduced by the modeling process to be isolated and evaluated. Models for both planar and hierarchical gate placement are presented.

关键词： analysis clustering critical-path gate-array GSI design partitioning

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SINGLE-BOARD SIMD PROCESSORS USING gate-array LSIS FOR PARALLEL-PROCESSING

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IEICE TRANSACTIONS ON ELECTRONICS 1993年第12期E76C卷 1827-1834页

作者： KONDO, T KIMURA, Y SONEHARA, N NTT LSI Laboratories Atugi Japan

We have developed an SIMD processor on a double-height VME board. We achieved a good balance between cost and performance by combining four identical gate-array LSIs in the processor array with a 16-bit digital signal processor (DSP), standard dynamic random-access memories (DRAMs) and other peripherals. The gate-array LSIs have 168-bit processing elements (PEs), each containing a one-bit processing block and a serial multiplier. This PE structure offers high-level bit processing capability and peak performance of 512 million operations per second (MOPS) for 8-bit multiply and accumulate operations. Effective performance of more than 300 MOPS for 8-bit array data processing is achieved by using an LSI structure tuned to the DRAM access rate, although the processing speed is reduced by the DRAM access bottleneck. The LSIs also have two unique additional hardware structures that speed up various array data processes. One is an inter-PE routing register array for supporting a transmission, rotation and memory access path. The other is a tree-structure network for propagating operations among PEs. With these cost-effective structures, the SIMD processor is expected to be widely used for two-dimensional data processing, such as image processing and pattern recognition.

关键词： PARALLEL PROCESSOR SIMD gate-array TREE NETWORK

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ARCHITECTURE DRIVEN LAYOUT SYNTHESIS TECHNIQUES FOR CA-TYPE FPGAS

ARCHITECTURE DRIVEN LAYOUT SYNTHESIS TECHNIQUES FOR CA-TYPE ...

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37th Midwest Symposium on Circuits and Systems

作者： DASARI, AK RAMINENI, N NAVEEN, B CHRZANOWSKAJESKE, M PORTLAND STATE UNIV DEPT ELECT ENGNPORTLANDOR 97207

ISBN: (纸本)0780324285

Predominantly local connections in new cellular architecture FPGAs present a challenge to CAD tool developers. In this paper we discuss new methodologies for low-level synthesis of digital circuits, to cellular architecture (CA) Field Programmable gate-arrays (FPGA). The design representation on logic level of abstraction is created or restructured in such a way that it resembles the architecture of FPGA as close as possible. The resulting structure is therefore easy to map, and a number of logic cells used for routing is minimized. Layout synthesis methods using different design representations are discussed and compared.

关键词： FPGA LAYOUT MAPPING FOLDING CELLULAR ARCHITECTURE gate-array

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