The problem of throughput maximisation in a wireless multiple-input multiple-output (MIMO) system using a quantised feedback, which is an appropriate model for practical systems with limited feedback capacity, is cons...
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The problem of throughput maximisation in a wireless multiple-input multiple-output (MIMO) system using a quantised feedback, which is an appropriate model for practical systems with limited feedback capacity, is considered. Unlike the ergodic capacity that can be achieved through power control only, maximising the throughput in the block fading channels is based on appropriate rate control strategy. The optimal quantised rate control design for general MIMO systems is formulated and a gradient descent search algorithm to find the optimal solution is employed. It is seen that the proposed quantised rate control scheme with only a few bits of feedback considerably improves the throughput of a MIMO system. With the same amount of feedback overhead, the proposed quantised rate control with constant power is compared with the optimal quantised power control strategy with an optimised constant rate, and the result demonstrates the importance of rate control in throughput maximisation. The effect of quantised rate control in MIMO systems employing different automatic repeat request schemes is also investigated.
This paper describes an ultra low power, motion estimation (ME) processor for MPEG2 HDTV resolution video. It adopts a gradientdescentsearch (GDS) algorithm that drastically reduces required computational power to 6...
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This paper describes an ultra low power, motion estimation (ME) processor for MPEG2 HDTV resolution video. It adopts a gradientdescentsearch (GDS) algorithm that drastically reduces required computational power to 6 GOPS. A SIMD datapath architecture optimized for the GDS algorithm decreases the clock frequency and operating voltage. A low power 3-port SRAM with a write-disturb-free cell array arrangement is newly designed for image data caches of the processor. The proposed ME processor contains 7-M transistors, integrated in 4.50 mm x 3.35 mm area using 0.13 mum CMOS technology. Estimated power consumption is less than 100 mW at 81 MHz@1.0 V. The processor is applicable to a portable HDTV system.
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