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hardware algorithm design and validation for nuclear radiation imaging based on Monte Carlo simulation

APPLIED RADIATION AND ISOTOPES 2024年 206卷 111228页

作者： Zou, Kefeng Wang, Lei Lu, Wei Feng, Penglei Chen, Junqiao Li, Haoxuan Chengdu Univ Technol Chengdu 610059 Sichuan Peoples R China

The nuclear radiation imaging technology, aimed at illustrating the position and distribution of radioactive sources, has undergone extensive research. By relying on a simulated radiation imaging system for data acquisition, we can significantly expedite the development cycle of these imaging instruments. Establishing simulated experimental scenarios and radiation imaging systems is of paramount significance in obtaining output signals for algorithmic testing and validation. This study is divided into two parts: simulation and hardware algorithm. In the simulation part, precise simulation of scintillation light transport in a crystal was achieved using the GEANT4 Monte Carlo simulation toolkit. A LaBr3(Ce) detector system was simulated by digitizing photon interactions. In the hardware algorithm part, a positioning algorithm based on a fully connected neural network was implemented and optimized using a heterogeneous distributed storage approach. The system validated and assessed the FPGA-based neural network gamma camera positioning algorithm, demonstrating significant consistency with computer -generated images in capturing the shape and dispersion of radioactive sources (planar, multi -point, and ring -shaped).

关键词： Monte Carlo simulation Nuclear radiation imaging FPGA hardware algorithm

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A hardware algorithm for modular division based on the extended euclidean algorithm

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IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS 1996年第11期E79D卷 1518-1522页

作者： Takagi, N Department of Information Engineering Nagoya University Nagoya-shi 464-01 Japan

A hardware algorithm for modular division is proposed. It is based on the extended Euclidean algorithm (EEA). The procedure for finding the multiplicative inverse in EEA is modified so that it calculates the quotient. Modular division is carried out through iteration of simple operations, such as shifts and additions. A redundant binary representation is employed so that additions are performed without carry propa- gation. An n-bit modular division is carried out in O(n) clock cycles. The length of each clock cycle is constant independent of n. A modular divider based on the algorithm has a bit-slice structure and is suitable for VLSI implementation.

关键词： Euclidean algorithm hardware algorithm modular arithmetic modular division redundant representation

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A MODULAR INVERSION hardware algorithm WITH A REDUNDANT BINARY REPRESENTATION

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IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS 1993年第8期E76D卷 863-869页

作者： TAKAGI, N Kyoto Univ Koyto Japan

A hardware algorithm for modular inversion is proposed. It is based on the extended Euclidean algorithm. All intermediate results are represented in a redundant binary representation with a digit set {0, 1, -1}. All addition/subtractions are performed without carry propagation. A modular inversion is carried out in O (n) clock cycles where n is the word length of the modulus. The length of each clock cycle is constant independent of n. A modular inverter based on the algorithm has a regular cellular array structure with a bit slice feature and is very suitable for VLSI implementation. Its amount of hardware is proportional to n.

关键词： COMPUTER ARITHMETIC COMPUTER CRYPTOGRAPH GREATEST COMMON DIVISOR (GCD) hardware algorithm MODULAR ARITHMETIC

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A hardware algorithm for modular multiplication/division

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IEEE TRANSACTIONS ON COMPUTERS 2005年第1期54卷 12-21页

作者： Kaihara, ME Takagi, N Nagoya Univ Dept Informat Engn Nagoya Aichi 4648603 Japan

A mixed radix-4/2 algorithm for modular multiplication/division suitable for VLSI implementation is proposed. The algorithm is based on Montgomery method for modular multiplication and on the extended Binary GCD algorithm for modular division. Both algorithms are modified and combined into the proposed algorithm so that almost all the hardware components are shared. The new algorithm carries out both calculations using simple operations such as shifts, additions, and subtractions. The radix-2 signed-digit representation is used to avoid carry propagation in all additions and subtractions. A modular multiplier/divider based on the algorithm performs an n-bit modular multiplication/division in O(n) clock cycles where the length of the clock cycle is constant and independent of n. The modular multiplier/divider has a linear array structure with a bit-slice feature and can be implemented with much smaller hardware than that necessary to implement both multiplier and divider separately.

关键词： computer arithmetic hardware algorithm modular multiplication modular division redundant representation cryptography

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A RADIX-4 MODULAR MULTIPLICATION hardware algorithm FOR MODULAR EXPONENTIATION

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IEEE TRANSACTIONS ON COMPUTERS 1992年第8期41卷 949-956页

作者： TAKAGI, N Dept. of Inf. Sci. Kyoto Univ. Japan Abstract Authors References Cited By Keywords Metrics Similar Download Citation Email Print Request Permissions

A fast radix-4 modular multiplication hardware algorithm is proposed. It is efficient for modular exponentiation with a large modulus used in public-key cryptosystems such as RSA cryptosystem. The operands and the result of multiplication which are intermediate results in modular exponentiation are represented in a redundant representation. The computation proceeds in serial-parallel fashion. Each subtraction for the division for residue calculation is embedded in the repeated multiply-addition. Each intermediate result is represented in a more redundant representation than that for the operands and the result, so that the number of the required addition/subtractions is reduced. All addition/subtractions are carried out without carry propagation. The algorithm is efficient for modular exponentiation, because only one carry propagate addition is required in the whole computation for a modular exponentiation. A serial-parallel modular multiplier based on the algorithm has a regular cellular array structure with a bit slice feature and is suitable for VLSI implementation. It seems easy to fabricate an RSA chip based on the multiplier using today's technology, which is expected to have a throughput of several times as large as that of the fastest actual RSA chip.

关键词： COMPUTER ARITHMETIC COMPUTER CRYPTOGRAPH hardware algorithm MODULAR MULTIPLICATION REDUNDANT REPRESENTATION VLSI

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A hardware algorithm for modular multiplication/division based on the extended Euclidean algorithm

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IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES 2005年第12期E88A卷 3610-3617页

作者： Kaihara, ME Takagi, N Nagoya Univ Dept Informat Engn Nagoya Aichi 4648603 Japan

A hardware algorithm for modular multiplication/division which performs modular division, Montgomery multiplication, and ordinary modular multiplication is proposed. The modular division in our algorithm is based on the extended Euclidean algorithm. We employ our newly proposed computation method that consists of processing the multiplier from the most significant digit first to calculate Montgomery multiplication. Finally, the ordinary modular multiplication is based on shift-and-add multiplication. Each of these three operations is carried out through the iteration of simple operations such as shifts and additions/subtractions. To avoid carry propagation in all additions and subtractions, the radix-2 signed-digit representation is employed. A modular multiplier/divider based on the algorithm has a linear array structure with a bit-slice feature and carries out n-bit modular multiplication/division in O(n) clock cycles, where the length of the clock cycle is constant and independent of n. This multiplier/divider can be implemented using a hardware amount only slightly larger than that of the modular divider.

关键词： modular arithmetic modular multiplication modular division Montgomery multiplication extended Euclidean algorithm hardware algorithm

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Fast hardware algorithm for Division in GF(2^m) Based on the Extended Euclid's algorithm With Parallelization of Modular Reductions

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2009年第8期56卷 644-648页

作者： Kobayashi, Katsuki Takagi, Naofumi Nagoya Univ Grad Sch Informat Sci Dept Informat Engn Nagoya Aichi 4648603 Japan

We propose a fast hardware algorithm for division in GF(2(m)) based on the extended Euclid's algorithm. The algorithm requires only one iteration to perform the operations that correspond to the ones performed in two iterations of previously reported division algorithms. Since the algorithm performs modular reductions in parallel by changing the order of execution of the operations, a circuit based on this algorithm has almost the same critical path delay as the previously proposed ones. The circuit computes division in m clock cycles, whereas the previously proposed circuits take 2m - 1 or more clock cycles.

关键词： Division Euclid's algorithm Galois field hardware algorithm

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A Multibit Left-Shift Modular Inverse hardware algorithm and its Implementation 53

A Multibit Left-Shift Modular Inverse Hardware Algorithm and...

引用

IEEE International Symposium on Circuits and Systems (IEEE ISCAS)

作者： Lu, Jinpeng Li, Shuguo Tsinghua Univ Inst Microelect Beijing 100084 Peoples R China

ISBN: (纸本)9781728192017

Modular inverse calculation has critical influence on the efficiency of public-key cryptographic algorithms such as RSA and elliptic curve cryptography. In this work, based on the original single bit left-shift modular inverse algorithm, a multibit left-shift modular inverse hardware algorithm and its implementation are proposed. Our proposed algorithm makes the operands able to be left-shifted by at most 8 bits within one clock cycle as depending on the output bits of the leading zero counting module. This can produce a reduction on the average computation cycles and absolute execution time. Simulations show that the proposed algorithm can reduces to 0.8n cycles from original 2n cycles for two n-bit operands and gains a 40% decrease in execution time, compared with the original algorithm.

关键词： left-shift modular inverse algorithm leading zero counting multibit shifting hardware algorithm

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A novel computationally adaptive hardware algorithm for video motion estimation

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IEICE TRANSACTIONS ON ELECTRONICS 1999年第9期E82C卷 1749-1754页

作者： Moshnyaga, VG Fukuoka Univ Dept Elect Engn & Comp Sci Fukuoka 8140180 Japan

A new hardware algorithm for the block matching video motion estimation is presented. The algorithm works in the full-search fashion but unlike the Full-Search Block Matching algorithm (FSBMA) it adjusts the number of computations dynamically to variable picture contents. Due to incorporated mechanism of data-driven thresholding, the proposed algorithm performs as four times as less operations comparing to the FSBMA while maintaining the same quality of results. Its hardware implementation is simple and compact. A supportive hardware design as well as simulation results on benchmarks are outlined.

关键词： video processing motion estimation hardware algorithm VLSI architecture

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High-Speed hardware algorithm for Continuous Mode Time-of-Flight Mass Spectrometry

High-Speed Hardware Algorithm for Continuous Mode Time-of-Fl...

引用

IEEE Latin American Symposium on Circuits and Systems

作者： Roman Held Josef Goette Marcel Jacomet Christian Tanner Marc Gonin Martin Tanner Bern University of Applied Sciences Engineering and Information Technology Tofwerk AG

ISBN: (纸本)9781467312073

We describe a real-time, high-speed data-acquisition and data-processing system for continuous mode time-of-flight mass spectrometers. To achieve data acquisition rates of 2 × 1.5 giga samples per second (GS/s), needed for the considered class of mass spectrometers, we implement the system as an FPGA-based hardware algorithm. We must solve two most challenging problems: First, the high-speed acquisition produces an enormous amount of data that we handle by on-the-fly data compression/uncompression to circumvent the memory-bandwidth restrictions. Second, the need for continuous acquisition of mass spectra and event-triggering ask for powerful hardware algorithms that allow to measure long signals that are composed of ultra-short signal pulses due to single aerosol- or nano particles.

关键词： hardware algorithm Mass spectroscopy Mass spectrometers time of flight mass spectroscopy mass spectra Time-of-flight mass spectrometers signal pulse

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