We describe a real-time, high-speed data-acquisition and data-processing system for continuous mode time-of-flight mass spectrometers. To achieve data acquisition rates of 2 × 1.5 giga samples per second (GS/s), ...
详细信息
ISBN:
(纸本)9781467312073
We describe a real-time, high-speed data-acquisition and data-processing system for continuous mode time-of-flight mass spectrometers. To achieve data acquisition rates of 2 × 1.5 giga samples per second (GS/s), needed for the considered class of mass spectrometers, we implement the system as an FPGA-based hardware algorithm. We must solve two most challenging problems: First, the high-speed acquisition produces an enormous amount of data that we handle by on-the-fly data compression/uncompression to circumvent the memory-bandwidth restrictions. Second, the need for continuous acquisition of mass spectra and event-triggering ask for powerful hardware algorithms that allow to measure long signals that are composed of ultra-short signal pulses due to single aerosol- or nano particles.
We present circuit implementations for computing exponentials and logarithms suitable for rapid single-flux-quantum (RSFQ) logic. We propose hardware algorithms based on the sequential table-lookup (STL) method using ...
详细信息
We present circuit implementations for computing exponentials and logarithms suitable for rapid single-flux-quantum (RSFQ) logic. We propose hardware algorithms based on the sequential table-lookup (STL) method using the radix-2 signed-digit representation that achieve high-throughput, digit-serial calculations. The circuits are implemented by processing elements formed in systolic-array-like, regularly-aligned pipeline structures. The processing elements are composed of adders, shifters, and readouts of precomputed constants. The iterative calculations are fully overlapped, and throughputs approach the maximum throughput of serial processing. The circuit size for calculating significand parts is estimated to be approximately 5-10 times larger than that of a bit-serial floating-point adder or multiplier.
The main contribution of this paper is to present a new hardware architecture for accelerating LZW compression using an FPGA. In the proposed architecture, we efficiently use dual-port block RAMs embedded in the FPGA ...
详细信息
ISBN:
(纸本)9783319495835;9783319495828
The main contribution of this paper is to present a new hardware architecture for accelerating LZW compression using an FPGA. In the proposed architecture, we efficiently use dual-port block RAMs embedded in the FPGA to implement a hash table that is used as a dictionary. Using independent two ports of the block RAM, reading and writing operations for the hash table are performed simultaneously. Additionally, we can read eight values in the hash table in one clock cycle by partitioning the hash table into eight tables. Since the proposed hardware implementation of LZW compression is compactly designed, we have succeeded in implementing 24 identical circuits in an FPGA, where the clock frequency of FPGA is 163.35 MHz. Our implementation of 24 proposed circuits attains a speed up factor of 23.51 times faster than a sequential LZW compression on a single CPU.
A 4-bit bit-slice multiplier for a 32-bit rapid single-flux-quantum (RSFQ) microprocessor is proposed. It carries out both signed and unsigned integer multiplication. A fully pipelined RSFQ logic design of the multipl...
详细信息
ISBN:
(纸本)9781467383486
A 4-bit bit-slice multiplier for a 32-bit rapid single-flux-quantum (RSFQ) microprocessor is proposed. It carries out both signed and unsigned integer multiplication. A fully pipelined RSFQ logic design of the multiplier using concurrent flow clocking consists of 33 stages and 17,551 Josephson junctions. The bit-slice approach simplifies the circuit complexity and reduces the hardware cost. For verification, an 8x8-bit 4-bit bit-slice multiplier based on the proposed algorithm has been designed and simulated using AIST 10-kA/cm(2) 1.0-mu m fabrication technology. The simulation result shows correct operation at 62.5 GHz.
The Collatz conjecture asserts that by a repeated iteration rule, the operation starting from any positive integer n, eventually produces the value of "1." The main contribution of this paper is to demonstra...
详细信息
The Collatz conjecture asserts that by a repeated iteration rule, the operation starting from any positive integer n, eventually produces the value of "1." The main contribution of this paper is to demonstrate a single-flux-quantum (SFQ)-based hardware algorithm that performs an exhaustive search to verify the Collatz conjecture. The circuit consists of a 16-bit integer register, a high-frequency clock generator, and a central processor. This design can perform at up to a maximum clock frequency of 90 GHz with a total power consumption of about 0.85 mW in simulation, based on the AIST 10 kA/cm(2) advanced Nb process. An LR-biasing approach further reduces the power consumption, whereas the computing speed can be accelerated by a factor of 20 when accelerating approaches are adopted. The assessments show that our design can process 2 x 10(7) numbers every second with an energy efficiency of about 5 x 10(10) numbers per Joule.
A variable soil pesticide injection system was developed for control of soil pesticide amount by PWMThe paper analyzed a algorithmic model of control system, and designed hardware, algorithm and control of soil pestic...
详细信息
ISBN:
(纸本)9783319483535
A variable soil pesticide injection system was developed for control of soil pesticide amount by PWMThe paper analyzed a algorithmic model of control system, and designed hardware, algorithm and control of soil pesticide,mainly software flow and a feedback control wayIn the paper, the variable-rate control system was consisted of infrared sensor, speed sensor, PWM valve, and pump motorAccording to the amount of soil pesticide information, controller can automatically control flow amount by adjusting solid solenoid valve and PWM valve based on working speed, which changes the pulse duty cycle to achieve the variable workInjection experiments of soil pesticide was pre-set different dosage, the results shown that pesticide amount was precise in fact, and the errors was less than 3.2 %The system could achieve variable rate injection of liquid pesticide into deep soil based on infrared sensorFitting equation of flow amount by adjusting PWM valve based on working speed could draw the R2 value of 0.935The chip can calculate the output PWM duty cycle according to the preset injection of soil pesticide amount after collected the speed of tractorThe feedback control is to regulate the PWM signal duty cycle according the real liquid flow obtained by the microcontroller chip which collected the output signal of liquid sensor which fixed on pesticide pipeline.
We propose a fast hardware algorithm for division in GF(2(m)) based on the extended Euclid's algorithm. The algorithm requires only one iteration to perform the operations that correspond to the ones performed in ...
详细信息
We propose a fast hardware algorithm for division in GF(2(m)) based on the extended Euclid's algorithm. The algorithm requires only one iteration to perform the operations that correspond to the ones performed in two iterations of previously reported division algorithms. Since the algorithm performs modular reductions in parallel by changing the order of execution of the operations, a circuit based on this algorithm has almost the same critical path delay as the previously proposed ones. The circuit computes division in m clock cycles, whereas the previously proposed circuits take 2m - 1 or more clock cycles.
A new efficient modular division algorithm suitable for systolic implementation and its systolic architecture is proposed in this article. With a new exit condition of while loop and a new updating method of a control...
详细信息
A new efficient modular division algorithm suitable for systolic implementation and its systolic architecture is proposed in this article. With a new exit condition of while loop and a new updating method of a control variable, the new algorithm reduces the average of iteration numbers by more than 14.3% compared to the algorithm proposed by Chen, Bai and Chen. Based on the new algorithm, we design a fast systolic architecture with an optimised core computing cell. Compared to the architecture proposed by Chen, Bai and Chen, our systolic architecture has reduced the critical path delay by about 18% and the total computational time for one modular division by almost 30%, with the cost of about 1% more cells. Moreover, by the addition of a flag signal and three logic gates, the proposed systolic architecture can also perform Montgomery modular multiplication and a fast unified modular divider/multiplier is realised.
This paper describes a video-based detection algorithm for parking spaces, the algorithm is based on a joint decision on multi-feature image processing algorithms, according to variance, correlation and edge-point den...
详细信息
ISBN:
(纸本)9781612848334
This paper describes a video-based detection algorithm for parking spaces, the algorithm is based on a joint decision on multi-feature image processing algorithms, according to variance, correlation and edge-point density data to determine the seize of parking spaces, and that with a higher recognition rate. We transplanted this algorithm into the FPGA platform. On that platform, who implemented the hardware algorithm, and then, based on the characteristics of the algorithm to improve and optimize it. At end of the test the hardware and software algorithms are compared.
Recent advances of superconducting single-flux-quantum (SFQ) circuit technology make it attractive to investigate computing systems using SFQ circuits, where arithmetic circuits play important roles In order to develo...
详细信息
Recent advances of superconducting single-flux-quantum (SFQ) circuit technology make it attractive to investigate computing systems using SFQ circuits, where arithmetic circuits play important roles In order to develop excellent SFQ arithmetic circuits, we have to design or select their underlying algorithms called hardware algorithms. from different point of view than CMOS circuits. because SFQ circuits work by pulse logic while CMOS circuits work by level logic In this paper. we compare implementations of hardware algorithms for addition by synchronous-clocking SFQ circuits We show that a set of individual bit-serial adders and Kogge-Stone adder are superior to others
暂无评论