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检索条件"主题词=hardware algorithm"
50 条 记 录,以下是11-20 订阅
High-Speed hardware algorithm for Continuous Mode Time-of-Flight Mass Spectrometry
High-Speed Hardware Algorithm for Continuous Mode Time-of-Fl...
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IEEE Latin American Symposium on Circuits and Systems
作者: Roman Held Josef Goette Marcel Jacomet Christian Tanner Marc Gonin Martin Tanner Bern University of Applied Sciences Engineering and Information Technology Tofwerk AG
We describe a real-time, high-speed data-acquisition and data-processing system for continuous mode time-of-flight mass spectrometers. To achieve data acquisition rates of 2 × 1.5 giga samples per second (GS/s), ... 详细信息
来源: 评论
High-Throughput Rapid Single-Flux-Quantum Circuit Implementations for Exponential and Logarithm Computation Using the Radix-2 Signed-Digit Representation
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IEICE TRANSACTIONS ON ELECTRONICS 2016年 第6期E99C卷 703-709页
作者: Tanaka, Masamitsu Takagi, Kazuyoshi Takagi, Naofumi Nagoya Univ Grad Sch Engn Nagoya Aichi 4648603 Japan Kyoto Univ Grad Sch Informat Kyoto 6068501 Japan
We present circuit implementations for computing exponentials and logarithms suitable for rapid single-flux-quantum (RSFQ) logic. We propose hardware algorithms based on the sequential table-lookup (STL) method using ... 详细信息
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An Efficient Implementation of LZW Compression in the FPGA  16th
An Efficient Implementation of LZW Compression in the FPGA
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16th International Conference on algorithms and Architectures for Parallel Processing (ICA3PP)
作者: Zhou, Xin Ito, Yasuaki Nakano, Koji Hiroshima Univ Dept Informat Engn Kagamiyama 1-4-1 Higashihiroshima 7398527 Japan
The main contribution of this paper is to present a new hardware architecture for accelerating LZW compression using an FPGA. In the proposed architecture, we efficiently use dual-port block RAMs embedded in the FPGA ... 详细信息
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A 4-bit Bit-Slice Multiplier for a 32-bit RSFQ Microprocessor  15
A 4-bit Bit-Slice Multiplier for a 32-bit RSFQ Microprocesso...
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15th International Superconductive Electronics Conference (ISEC)
作者: Tang, Guang-Ming Takagi, Kazuyoshi Takagi, Naofumi Kyoto Univ Grad Sch Informat Dept Commun & Comp Engn Kyoto Japan
A 4-bit bit-slice multiplier for a 32-bit rapid single-flux-quantum (RSFQ) microprocessor is proposed. It carries out both signed and unsigned integer multiplication. A fully pipelined RSFQ logic design of the multipl... 详细信息
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Demonstration of Bit-Serial SFQ-Based Computing for Integer Iteration algorithms
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IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY 2015年 第3期25卷
作者: Xu, Qiuyun Peng, Xizhu Ortlepp, Thomas Yamanashi, Yuki Yoshikawa, Nobuyuki Yokohama Natl Univ Dept Elect & Comp Engn Yokohama Kanagawa 2408501 Japan CiS Res Inst Microsensor Syst & Photovolta D-99099 Erfurt Germany
The Collatz conjecture asserts that by a repeated iteration rule, the operation starting from any positive integer n, eventually produces the value of "1." The main contribution of this paper is to demonstra... 详细信息
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Development of Variable Rate System for Disinfection Based on Injection Technique
Development of Variable Rate System for Disinfection Based o...
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The 9th International Conference on Computer and Computing Technologies in Agriculture (CCTA 2015)
作者: Wei Ma Xiu Wang Lijun Qi Wei Zou College of Engineering China Agricultural University National Engineering Research Center of Intelligent Equipment for Agriculture
A variable soil pesticide injection system was developed for control of soil pesticide amount by PWMThe paper analyzed a algorithmic model of control system, and designed hardware, algorithm and control of soil pestic... 详细信息
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Fast hardware algorithm for Division in GF(2m) Based on the Extended Euclid's algorithm With Parallelization of Modular Reductions
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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2009年 第8期56卷 644-648页
作者: Kobayashi, Katsuki Takagi, Naofumi Nagoya Univ Grad Sch Informat Sci Dept Informat Engn Nagoya Aichi 4648603 Japan
We propose a fast hardware algorithm for division in GF(2(m)) based on the extended Euclid's algorithm. The algorithm requires only one iteration to perform the operations that correspond to the ones performed in ... 详细信息
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Efficient algorithm and systolic architecture for modular division
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INTERNATIONAL JOURNAL OF ELECTRONICS 2011年 第6期98卷 813-823页
作者: Chen, Chuanpeng Qin, Zhongping Huazhong Univ Sci & Technol Sch Software Engn Wuhan 430074 Peoples R China Wuhan Univ Sch Comp Wuhan 430072 Peoples R China
A new efficient modular division algorithm suitable for systolic implementation and its systolic architecture is proposed in this article. With a new exit condition of while loop and a new updating method of a control... 详细信息
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FPGA-based parking space image detection algorithm
FPGA-based parking space image detection algorithm
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2011 4th IEEE International Conference on Computer Science and Information Technology(ICCSIT 2011)
作者: Yanwu Gao Bin Zhang Lili Gan Bingchen Zhao Department of Information Science and Technology Xing Tai University
This paper describes a video-based detection algorithm for parking spaces, the algorithm is based on a joint decision on multi-feature image processing algorithms, according to variance, correlation and edge-point den... 详细信息
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Comparisons of Synchronous-Clocking SFQ Adders
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IEICE TRANSACTIONS ON ELECTRONICS 2010年 第4期E93C卷 429-434页
作者: Takagi, Naofumi Tanaka, Masamitsu Nagoya Univ Dept Informat Engn Nagoya Aichi 4648603 Japan
Recent advances of superconducting single-flux-quantum (SFQ) circuit technology make it attractive to investigate computing systems using SFQ circuits, where arithmetic circuits play important roles In order to develo... 详细信息
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