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A hardware implementation of realloc function

INTEGRATION-THE VLSI JOURNAL 1999年第2期28卷 173-184页

作者： Srisa-an, W Lo, CTD Chang, JM IIT Dept Comp Sci Chicago IL 60616 USA

The memory intensive nature of object-oriented languages such as C + + and Java has created the need of a high-performance dynamic memory management. Object-oriented applications often generate higher memory intensity in the heap region. Thus, high-performance memory manager is needed to cope with such applications. As today's VLSI technology advances, it becomes more and more attractive to map basic software algorithms such as malloc(),free(), and realloc() into hardware. This paper presents a hardware design of realloc function that fully utilizes the advantage of combinational logic. There are two steps needed to complete a reallocation process: (a) try to reallocate on the original memory block and (b) if (a) failed, allocate another memory block and copy the contents of the original block to this new location. In our scheme, (a) can be done in constant time. For (b), the allocation of new memory block and the deallocation of original block are done in constant time. The hardware complexity of proposed scheme (i.e. X-unit, RS-unit, and ESG-unit) is O(n), where n represents the size of bit-map. (C) 1999 Published by Elsevier Science B.V. All rights reserved.

关键词： hardware algorithms VLSI systems dynamic memory management algorithms expand() realloc()

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An Efficient Match Search Approach Using Two-Dimensional Hash Function in hardware-Based Dictionary Compression

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JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS 2019年第6期28卷 1950106.1-1950106.16页

作者： Dong, Qian Li, Bing Southeast Univ Sch Integrated Circuits Sipailou 2 Nanjing 210096 Jiangsu Peoples R China Southeast Univ Chengxian Coll Dongda Rd 6 Nanjing 210088 Jiangsu Peoples R China

The hardware-based dictionary compression is widely adopted for high speed requirement of real-time data processing. Hash function helps to manage large dictionary to improve compression ratio but is prone to collisions, so some phrases in match search result are not true matches. This paper presents a novel match search approach called dual chaining hash refining, which can improve the efficiency of match search. From the experimental results, our method showed obvious advantage in compression speed compared with other approach that utilizes single hash function described in the previous publications.

关键词： Dual chaining hash refining dictionary compression match search hash collision hardware algorithms

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Object resizing and reclamation through the use of hardware bit-maps

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MICROPROCESSORS AND MICROSYSTEMS 2002年第9-10期25卷 459-467页

作者： Srisa-an, W Lo, CTD Chang, JM IIT Dept Comp Sci Chicago IL 60616 USA

The memory intensive nature of object-oriented languages such as C++ and Java has created the need of a high-performance dynamic memory management. Object-oriented applications often generate higher memory intensity in the heap region. Thus, high-performance memory manager is needed to cope with such applications. As today's VLSI technology advances, it becomes more and more attractive to map software algorithms such as malloc(), free(), realloc(), and garbage collection into hardware. This paper presents hardware designs of realloc function and sweeping function (for mark and sweep garbage collection) that fully utilize the advantages of combinational logic. In our scheme, the reallocation on the original block can be done in constant time. If the reallocation on the original block is not possible, the previously proposed malloc() and free() can be used to move the contents to a new location. For the sweeping function, the bit-sweeper can detect and sweep the garbage in constant time. Since the sweeping phase often consumes more time than the marking phase, the garbage collection time can be substantially improved. The hardware complexity of proposed scheme (i.e. X-Unit, RS-unit, ESG-unit, and bit-sweeper) is O(n), where n represents the size of bit-map. (C) 2002 Elsevier Science B.V. All rights reserved.

关键词： hardware algorithms VLSI systems dynamic memory management algorithms expand() realloc() mark and sweep garbage collection

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hardware ALGORITHM FOR NET EXTRACTION

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COMPUTER-AIDED DESIGN 1987年第7期19卷 347-354页

作者： KANE, R SAHNI, S UNIV MINNESOTA DEPT COMP SCIMINNEAPOLISMN 55455

An algorithm for net extraction is developed that is suitable for hardware implementation. The algorithm has three components: sort, pair generation, and net construction. The first two are systolic and may be impleme... 详细信息

关键词： net extraction systolic algorithms hardware algorithms

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hardware Based Parallel Phrase Matching Engine in Dictionary Compressor

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IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS 2018年第12期E101D卷 2968-2970页

作者： Dong, Qian Southeast Univ Sch Integrated Circuits Nanjing 210046 Jiangsu Peoples R China

A parallel phrase matching (PM) engine for dictionary compression is presented. hardware based parallel chaining hash can eliminate erroneous PM results raised by hash collision;while newly-designed storage architectu... 详细信息

关键词： parallel chaining hash dictionary compression phrase match hash collision hardware algorithms

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DYNAMIC hardware-ORIENTED ALGORITHM FOR ANGLE OF ARRIVAL POSITIONING TECHNIQUE

DYNAMIC HARDWARE-ORIENTED ALGORITHM FOR ANGLE OF ARRIVAL POS...

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IEEE International Conference on Signal Processing and Communications

作者： Salamah, M. Doukhnitch, E. Bayramer, C. Eastern Mediterranean Univ Dept Comp Engn KKTC Mersin 10 Turkey

ISBN: (纸本)9781424412358

There is an increasing demand for finding a mobile location in areas such as robotics applications, electronic warfare positioning, wireless communication systems and vehicle security. Angle of Arrival (AOA) is one of the key techniques in wireless location estimation. Location estimation is done by using standard triangulation operations that are usually implemented in software. In this paper, we present a new hardware-oriented algorithm that uses only simple shift and add operations in the computation and therefore can be easily implemented in hardware. The comparison between this method and the conventional AOA based positioning technique is discussed in terms of computational cost (required number of operations). The results show that the proposed algorithm outperforms the traditional one in terms of both software and hardware implementations points of views.

关键词： Positioning angle of arrival hardware algorithms

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Analysis of Single-Chip hardware Support for Mobile and Embedded Applications

Analysis of Single-Chip Hardware Support for Mobile and Embe...

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IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM)

作者： Perera, Darshika G. Li, Kin Fun CMC Microsyst Kingston ON Canada Univ Victoria Dept Elect & Comp Engn Victoria BC V8W 2Y2 Canada

ISBN: (纸本)9781479915019

As mobile and handheld devices are gaining popularity, many applications have found their ways into these devices. In order to use these mobile systems effectively and efficiently, it is important to optimize their embedded software and hardware. This work focuses on hardware support for mobile and embedded applications in single-chip format so as to reduce the hardware footprint as required in these handheld devices. Applications specific circuits, single-core microprocessor, and field programmable gate arrays are presented, and their strengths and weaknesses are discussed. Reconfigurable computing systems, specifically FPGA-based approaches, are introduced, and techniques for their reconfiguration are analyzed. It is concluded that reconfigurable FPGA-based system is currently the best option to deliver embedded applications that have stringent requirements.

关键词： mobile applications embedded devices hardware algorithms hardware support reconfigurable computing field programmable arrays single-chip systems

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Optimal Parallel hardware K-Sorter and TopK-Sorter, with FPGA implementations 14

Optimal Parallel Hardware K-Sorter and TopK-So...

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IEEE 14th International Symposium on Parallel and Distributed Computing (ISPDC)

作者： Matsumoto, Naoyuki Nakano, Koji Ito, Yasuaki Hiroshima Univ Dept Informat Engn Kagamiyama 1-4-1 Higashihiroshima 7398527 Japan

ISBN: (纸本)9781467371483

This paper presents a FIFO-based parallel merge sorter optimized for the latest FPGA. More specifically, we show a sorter that sorts K keys in latency K+ log(2) K-1 using log(2) K comparators. It uses K M + log(2) K+ log(2) M-1 memory blocks with capacity M to implement FIFOs. It receives K keys one by one in every clock cycle and outputs the sorted sequence of them from K + log(2) K -1 clock cycles after. Since K clock cycles are necessary to input all K keys, our sorter is almost optimal in terms of the latency. Also, since the total FIFO capacity is only K+ M log(2) K+ M log(2) M-M and at least K keys must be stored in the sorter, our sorter is also almost optimal in terms of the total FIFO capacity if M is small. This paper also presents topK-sorter, which outputs top K keys in N input keys for any large N. Our topK-sorter runs in latency N + log(2) K using log(2) K + 1 comparators. It uses memory blocks of size M and the total FIFO capacity is only 2K + M log(2) K+ M log(2) M-2M. Quite surprisingly, the total FIFO capacity is independent of N. Also, since the latency must be at least N, that of our topK-sorter is almost optimal in terms of the latency. Finally, we have implemented our K-sorter and topK-sorter in a Xilinx Virtex-7 FPGA using built-in Distributed RAMs and Block RAMs. The implementation results show that our K-sorter reduces the used memory resources by half, and both K-sorter and topK-sorter are practical and efficient.

关键词： big data data mining hardware algorithms parallel sorting algorithms

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A hardware implementation of Realloc function

A hardware implementation of Realloc function

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IEEE-Computer-Society Workshop on VLSI (WVLSI 99) - System Level Design

作者： Srisa-an, W Lo, CTD Chang, JM IIT Dept Comp Sci Chicago IL 60616 USA

ISBN: (纸本)0769501524

The memory intensive nature of object-oriented languages such as C++ and Java has created the need of a high-performance dynamic memory management. Object-oriented applications often generate higher memory intensity in the heap region. Thus, high-performance memory manager is needed to cope with such applications. As today's VLSI technology advances, it becomes more and more attractive to map basic software algorithms such as malloc(), free(), and realloc() into hardware. This paper presents a hardware design of realloc function that fully utilizes the advantage of combinational logic. There are two steps needed to complete a reallocation process: (a) try to reallocate on the original memory block and (b) if (a)failed, allocate another memory block and copy the contents of the original block to this new location. In our scheme, (a) can be done in constant time. For (b), the allocation of new memory block and the deallocation of original block are done in constant time. The hardware complexity of proposed scheme (i.e. X-unit, RS-unit, and ESG-unit) is O(n), where n represents the size of bit-map.

关键词： hardware algorithms VLSI systems dynamic memory management algorithms expand realloc

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A hardware sorter for almost sorted sequences, with FPGA implementations 4

A hardware sorter for almost sorted sequences, with FPGA imp...

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4th International Symposium on Computing and Networking (CANDAR)

作者： Harada, Naoaki Matsumoto, Naoyuki Nakano, Koji Ito, Yasuaki Hiroshima Univ Dept Informat Engn Kagamiyama 1-4-1 Higashihiroshima 7398527 Japan

ISBN: (纸本)9781509026555

Suppose that a sequence of sensing data with timestamps are transferred asynchronously. Some of sensing data may be delayed by some period of time and the sequence is not in proper increasing order of timestamps. A sequence of timestamps t(0), t(1), . . . , tn-1 is d-sorted if t(i) < t(j) holds for all pairs of timestamps ti and tj such that j-i >= d. Intuitively, a parameter d corresponds to the maximum period of delay and we can say that a d-sorted sequence is almost sorted if d is small. The main contribution of this paper is to show a hardware d-sorter that sorts a d-sorted sequence of timestamps, and to implement it in the FPGA. Our idea for a hardware d-sorter is to use a merge-based algorithm using FIFOs. This hardware algorithm takes n + 2d + log(2) d clock cycles using log2 d comparators for a d-sorted sequence of n timestamps. Since Omega(n log d) comparisons are necessary, it is cost optimal and attains optimal speedup. We also present the cyclic comparison method to reduce the number of bits in timestamps to be sorted. The experimental results show that the FPGA implementation is 5-10 time faster than a sequential d-sort program using a single CPU. Also, when d = 2048, our merge-based d-sorter is 2.59 times faster than a previously published hardware heap-based d-sorter, which takes 2n + 2d clock cycles.

关键词： parallel sorting algorithms hardware algorithms timestamp sorter block RAMs

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