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A Simplified Correlation Index for Fast Real-Time Pulse Shape Recognition

SENSORS 2022年第20期22卷 7697-7697页

作者： Cicuttin, Andres Morales, Ivan Rene Crespo, Maria Liz Carrato, Sergio Garcia, Luis Guillermo Molina, Romina Soledad Valinoti, Bruno Kamdem, Jerome Folla Abdus Salam Int Ctr Theoret Phys ICTP Multidisciplinary Lab I-34151 Trieste Italy Univ Trieste UNITS Dipartimento Ingn & Architettura I-34127 Trieste Italy Univ Yaounde I Dept Phys POB 812 Yaounde 222 Cameroon

A simplified correlation index is proposed to be used in real-time pulse shape recognition systems. This index is similar to the classic Pearson's correlation coefficient, but it can be efficiently implemented in FPGA devices with far fewer logic resources and excellent performance. Numerical simulations with synthetic data and comparisons with the Pearson's correlation show the suitability of the proposed index in applications such as the discrimination and counting of pulses with a predefined shape. Superior performance is evident in signal-to-noise ratio scenarios close to unity. FPGA implementation of Person's method and the proposed correlation index have been successfully tested and the main results are summarized.

关键词： pulse shape recognition correlation hardware algorithms SoC FPGA digital signal processing pattern recognition digital pulse processing pulse counting noise reduction

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An Efficient Match Search Approach Using Two-Dimensional Hash Function in hardware-Based Dictionary Compression

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JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS 2019年第6期28卷 1950106.1-1950106.16页

作者： Dong, Qian Li, Bing Southeast Univ Sch Integrated Circuits Sipailou 2 Nanjing 210096 Jiangsu Peoples R China Southeast Univ Chengxian Coll Dongda Rd 6 Nanjing 210088 Jiangsu Peoples R China

The hardware-based dictionary compression is widely adopted for high speed requirement of real-time data processing. Hash function helps to manage large dictionary to improve compression ratio but is prone to collisions, so some phrases in match search result are not true matches. This paper presents a novel match search approach called dual chaining hash refining, which can improve the efficiency of match search. From the experimental results, our method showed obvious advantage in compression speed compared with other approach that utilizes single hash function described in the previous publications.

关键词： Dual chaining hash refining dictionary compression match search hash collision hardware algorithms

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hardware Based Parallel Phrase Matching Engine in Dictionary Compressor

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IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS 2018年第12期E101D卷 2968-2970页

作者： Dong, Qian Southeast Univ Sch Integrated Circuits Nanjing 210046 Jiangsu Peoples R China

A parallel phrase matching (PM) engine for dictionary compression is presented. hardware based parallel chaining hash can eliminate erroneous PM results raised by hash collision;while newly-designed storage architectu... 详细信息

关键词： parallel chaining hash dictionary compression phrase match hash collision hardware algorithms

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A Fast and Scalable FPGA-Based Parallel Processing Architecture for K-Means Clustering for Big Data Analysis

A Fast and Scalable FPGA-Based Parallel Processing Architect...

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IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM)

作者： Raghavan, Ramprasad Perera, Darshika G. Univ Colorado Dept Elect & Comp Engn Colorado Springs CO 80933 USA

ISBN: (纸本)9781538607008

The exponential growth of complex, heterogeneous, dynamic, and unbounded data, generated by a variety of fields including health, genomics, physics, climatology, and social networks pose significant challenges in data processing and desired speed-performance. Existing processor-based software-only algorithms are incapable of analyzing and processing this enormous amount of data, efficiently and effectively. Consequently, some kind of hardware support is desirable to overcome the challenges in analyzing big data. Big data analytics involves many important data mining tasks including clustering, which categorizes the data into meaningful groups based on the similarity or dissimilarity among objects. In this research work, we introduce an efficient FPGA-based parallel processing architecture for K-means Clustering, one of the most popular clustering algorithms. Experiments are performed on a benchmark dataset to evaluate the feasibility and efficiency of our hardware design. Our hardware architecture is generic, parameterized, and scalable to support larger and varying datasets as well as a varying number of clusters. Our hardware configuration with 32 processing elements (PEs) achieved 368 times speedup compared to its software counterpart.

关键词： Big data analysis parallel processing architecture FPGAs K-Means clustering embedded hardware hardware algorithms data mining

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A hardware sorter for almost sorted sequences, with FPGA implementations 4

A hardware sorter for almost sorted sequences, with FPGA imp...

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4th International Symposium on Computing and Networking (CANDAR)

作者： Harada, Naoaki Matsumoto, Naoyuki Nakano, Koji Ito, Yasuaki Hiroshima Univ Dept Informat Engn Kagamiyama 1-4-1 Higashihiroshima 7398527 Japan

ISBN: (纸本)9781509026555

Suppose that a sequence of sensing data with timestamps are transferred asynchronously. Some of sensing data may be delayed by some period of time and the sequence is not in proper increasing order of timestamps. A sequence of timestamps t(0), t(1), . . . , tn-1 is d-sorted if t(i) < t(j) holds for all pairs of timestamps ti and tj such that j-i >= d. Intuitively, a parameter d corresponds to the maximum period of delay and we can say that a d-sorted sequence is almost sorted if d is small. The main contribution of this paper is to show a hardware d-sorter that sorts a d-sorted sequence of timestamps, and to implement it in the FPGA. Our idea for a hardware d-sorter is to use a merge-based algorithm using FIFOs. This hardware algorithm takes n + 2d + log(2) d clock cycles using log2 d comparators for a d-sorted sequence of n timestamps. Since Omega(n log d) comparisons are necessary, it is cost optimal and attains optimal speedup. We also present the cyclic comparison method to reduce the number of bits in timestamps to be sorted. The experimental results show that the FPGA implementation is 5-10 time faster than a sequential d-sort program using a single CPU. Also, when d = 2048, our merge-based d-sorter is 2.59 times faster than a previously published hardware heap-based d-sorter, which takes 2n + 2d clock cycles.

关键词： parallel sorting algorithms hardware algorithms timestamp sorter block RAMs

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RAMPS: A Reconfigurable Architecture for Minimal Perfect Sequencing

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IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 2016年第10期27卷 3029-3043页

作者： Nelson, Chad Townsend, Kevin R. Attia, Osama G. Jones, Phillip H. Zambreno, Joseph Iowa State Univ Dept Elect & Comp Engn Ames IA 50011 USA

The alignment of many short sequences of DNA, called reads, to a long reference genome is a common task in molecular biology. When the problem is expanded to handle typical workloads of billions of reads, execution time becomes critical. In this paper we present a novel reconfigurable architecture for minimal perfect sequencing (RAMPS). While existing solutions attempt to align a high percentage of the reads using a small memory footprint, RAMPS focuses on performing fast exact matching. Using the human genome as a reference, RAMPS aligns short reads hundreds of thousands of times faster than current software implementations such as SOAP2 or Bowtie, and about a thousand times faster than GPU implementations such as SOAP3. Whereas other aligners require hours to preprocess reference genomes, RAMPS can preprocess the reference human genome in a few minutes, opening the possibility of using new reference sources that are more genetically similar to the newly sequenced data.

关键词： hardware algorithms FPGAs bioinformatics short-read aligner convey HC-2 reconfigurable hardware

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Optimal Parallel hardware K-Sorter and TopK-Sorter, with FPGA implementations 14

Optimal Parallel Hardware <i>K</i>-Sorter and Top<i>K</i>-So...

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IEEE 14th International Symposium on Parallel and Distributed Computing (ISPDC)

作者： Matsumoto, Naoyuki Nakano, Koji Ito, Yasuaki Hiroshima Univ Dept Informat Engn Kagamiyama 1-4-1 Higashihiroshima 7398527 Japan

ISBN: (纸本)9781467371483

This paper presents a FIFO-based parallel merge sorter optimized for the latest FPGA. More specifically, we show a sorter that sorts K keys in latency K+ log(2) K-1 using log(2) K comparators. It uses K M + log(2) K+ log(2) M-1 memory blocks with capacity M to implement FIFOs. It receives K keys one by one in every clock cycle and outputs the sorted sequence of them from K + log(2) K -1 clock cycles after. Since K clock cycles are necessary to input all K keys, our sorter is almost optimal in terms of the latency. Also, since the total FIFO capacity is only K+ M log(2) K+ M log(2) M-M and at least K keys must be stored in the sorter, our sorter is also almost optimal in terms of the total FIFO capacity if M is small. This paper also presents topK-sorter, which outputs top K keys in N input keys for any large N. Our topK-sorter runs in latency N + log(2) K using log(2) K + 1 comparators. It uses memory blocks of size M and the total FIFO capacity is only 2K + M log(2) K+ M log(2) M-2M. Quite surprisingly, the total FIFO capacity is independent of N. Also, since the latency must be at least N, that of our topK-sorter is almost optimal in terms of the latency. Finally, we have implemented our K-sorter and topK-sorter in a Xilinx Virtex-7 FPGA using built-in Distributed RAMs and Block RAMs. The implementation results show that our K-sorter reduces the used memory resources by half, and both K-sorter and topK-sorter are practical and efficient.

关键词： big data data mining hardware algorithms parallel sorting algorithms

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Analysis of Single-Chip hardware Support for Mobile and Embedded Applications

Analysis of Single-Chip Hardware Support for Mobile and Embe...

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IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM)

作者： Perera, Darshika G. Li, Kin Fun CMC Microsyst Kingston ON Canada Univ Victoria Dept Elect & Comp Engn Victoria BC V8W 2Y2 Canada

ISBN: (纸本)9781479915019

As mobile and handheld devices are gaining popularity, many applications have found their ways into these devices. In order to use these mobile systems effectively and efficiently, it is important to optimize their embedded software and hardware. This work focuses on hardware support for mobile and embedded applications in single-chip format so as to reduce the hardware footprint as required in these handheld devices. Applications specific circuits, single-core microprocessor, and field programmable gate arrays are presented, and their strengths and weaknesses are discussed. Reconfigurable computing systems, specifically FPGA-based approaches, are introduced, and techniques for their reconfiguration are analyzed. It is concluded that reconfigurable FPGA-based system is currently the best option to deliver embedded applications that have stringent requirements.

关键词： mobile applications embedded devices hardware algorithms hardware support reconfigurable computing field programmable arrays single-chip systems

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FPGA-Based Real-Time Swept-Source OCT Systems for B-Scan Live-Streaming or Volumetric Imaging

FPGA-Based Real-Time Swept-Source OCT Systems for B-Scan Liv...

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Conference on Optical Coherence Tomography and Coherence Domain Optical Methods in Biomedicine XVII at the SPIE Photonics West Symposia

作者： Bandi, Vinzenz Goette, Josef Jacomet, Marcel von Niederhaeusern, Tim Bachmann, Adrian H. Duelk, Marcus Bern Univ Appl Sci HuCE MicroLab Bfh Ti CH-2501 Biel Switzerland

ISBN: (纸本)9780819493408

We have developed a Swept-Source Optical Coherence Tomography (Ss-OCT) system with high-speed, real-time signal processing on a commercially available Data-Acquisition (DAQ) board with a Field-Programmable Gate Array (FPGA). The Ss-OCT system simultaneously acquires OCT and k-clock reference signals at 500 MS/s. From the k-clock signal of each A-scan we extract a remap vector for the k-space linearization of the OCT signal. The linear but oversampled interpolation is followed by a 2048-point FFT, additional auxiliary computations, and a data transfer to a host computer for real-time, live-streaming of B-scan or volumetric C-scan OCT visualization. We achieve a 100 kHz A-scan rate by parallelization of our hardware algorithms, which run on standard and affordable, commercially available DAQ boards. Our main development tool for signal analysis as well as for hardware synthesis is MATLAB (R) with add-on toolboxes and 3rd-party tools.

关键词： hardware synthesis hardware algorithms MATLAB/SIMULINK signal processing parallelization OCT B-scan C-scan live-streaming

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Analysis of Single-Chip hardware Support for Mobile and Embedded Applications

Analysis of Single-Chip Hardware Support for Mobile and Embe...

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IEEE Pacific Rim Conference on Communications, Computers and Signal Processing

作者： Darshika G. Perera Kin Fun Li CMC Microsystems Kingston Canada Department of Electrical and Computer Engineering University of Victoria Victoria Canada

ISBN: (纸本)9781479915002

关键词： mobile applications embedded devices hardware algorithms hardware support reconfigurable computing field programmable arrays single-chip systems

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