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General approach to simple algorithms for 2-D positioning techniques in cellular networks

COMPUTER COMMUNICATIONS 2008年第10期31卷 2185-2194页

作者： Doukhnitch, E. Salamah, M. Eastern Mediterranean Univ Dept Comp Engn TR-10 Famagusta Trnc Mersin Turkey

Finding the location of an object is one of the important features of autonomous and the 3G/4G wireless communication systems. Many valuable location based services can be enabled by this feature. Position estimation from Time of Arrival (TOA), Time Difference of Arrival (TDOA), and Angle of Arrival (AOA) measurements are the commonly used techniques. These approaches use the location parameters received from different sources, and they are based on intersections of circles, hyperbolas, and lines, respectively. The location is determined using standard complex computation methods that are usually implemented in software. In this paper, we propose a general approach to design new hardware-oriented algorithms that use only simple add and shift operations in the computation and therefore can be easily implemented in hardware or firmware. In addition to their implementation simplicity, the proposed algorithms outperform the conventional ones in terms of the required number of operations for a specific accuracy level. (C) 2008 Elsevier B.V. All rights reserved.

关键词： positioning angle of arrival time of arrival hardware algorithms wireless networks

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APPROACHING ENCRYPTION AT ISDN SPEED USING PARTIAL PARALLEL MODULUS MULTIPLICATION

MICROPROCESSING AND MICROPROGRAMMING

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MICROPROCESSING AND MICROPROGRAMMING 1990年第3期29卷 177-184页

作者： POSCH, KC POSCH, R GRAZ TECH UNIV DEPT APPL INFORMAT PROC & COMMUN TECHNOLA-8010 GRAZAUSTRIA

Public key systems using modulus arithmetic are quite safe mechanisms for a variety of cryptographic applications. Their main problem lies in the very long integer arithmetic. In cryptosystems usually serial-parallel multiplication is employed. Serial-parallel multiplication slows down the encryption to the order of k , where k is log 2 ( n ), and n is the modulus. This paper demonstrates a method of using parallel multiplication schemes at the order of log ( k ) in combination with incomplete modulus reduction. This method calls for redundant number representations. With this background, the problem of designing a quasi optimal scheme fitting into a defined chip area is elaborated. The combination of two methods, partial parallel multiplication in redundant number representations and incomplete modulus reduction at fully completed multiplication steps only, seems to allow for RSA encryption at ISDN speed and higher.

关键词： Public key cryptosystems Cryptography hardware algorithms VLSI Parallel multiplier High speed multiplier

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Sign detection in residue arithmetic units

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JOURNAL OF SYSTEMS ARCHITECTURE 1998年第3期45卷 251-258页

作者： Giuseppe, A Martinelli, E Univ Pisa Dipartimento Ingn Informaz I-56100 Pisa Italy Univ Siena Dipartimento Ingn Informaz I-53100 Siena Italy

The parallelism of computation, that characterizes some operations in residue number systems (RNS), is heavily reduced in operations as division, magnitude and sign detection, since numbers must be converted to the weighted system thus reducing efficiency, in spite of the efforts to speed up the conversion. In this work the problem of detecting the sign of numbers represented in RNS is considered and a procedure is devised, which keeps numbers in residue notation, and requires a redundant modulus m(p+1) greater than or equal to 2. A sign detecting circuit is also designed that, merely to speed up the operation, exploits a further redundant modulus m(r) greater than or equal to p in the signed number representation. Circuit response time is evaluated, both from the complexity point of view and in a finite case, where 50 gate delays are estimated for a range [-2(64), 2(64) - 1]. (C) 1998 Elsevier Science B.V. All rights reserved.

关键词： residue number systems residue arithmetic units sign detection base extension hardware algorithms

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A FAST VLSI SOLUTION FOR APPROXIMATE STRING MATCHING

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INTEGRATION-THE VLSI JOURNAL 1992年第2期13卷 195-206页

作者： GROSSI, R UNIV PISA DIPARTIMENTO INFORMATI-56125 PISAITALY

A simple hardware algorithm is proposed for the approximate string matching problem, where a string is searched in a large, flat text with a bounded number of insertions, deletions and substitutions. The employed interconnection network is a classical mesh-of-trees, augmented with trees along the main diagonals of the mesh. The area and time bounds are shown, and compared favorably with previous solutions in many cases.

关键词： APPROXIMATE STRING MATCHING DYNAMIC PROGRAMMING hardware algorithms MESH-OF-TREES VLSI IMPLEMENTATION

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RAMPS: A Reconfigurable Architecture for Minimal Perfect Sequencing

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IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 2016年第10期27卷 3029-3043页

作者： Nelson, Chad Townsend, Kevin R. Attia, Osama G. Jones, Phillip H. Zambreno, Joseph Iowa State Univ Dept Elect & Comp Engn Ames IA 50011 USA

The alignment of many short sequences of DNA, called reads, to a long reference genome is a common task in molecular biology. When the problem is expanded to handle typical workloads of billions of reads, execution time becomes critical. In this paper we present a novel reconfigurable architecture for minimal perfect sequencing (RAMPS). While existing solutions attempt to align a high percentage of the reads using a small memory footprint, RAMPS focuses on performing fast exact matching. Using the human genome as a reference, RAMPS aligns short reads hundreds of thousands of times faster than current software implementations such as SOAP2 or Bowtie, and about a thousand times faster than GPU implementations such as SOAP3. Whereas other aligners require hours to preprocess reference genomes, RAMPS can preprocess the reference human genome in a few minutes, opening the possibility of using new reference sources that are more genetically similar to the newly sequenced data.

关键词： hardware algorithms FPGAs bioinformatics short-read aligner convey HC-2 reconfigurable hardware

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PMAC - A POLYGON MATCHING CHIP

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INTERNATIONAL JOURNAL OF PATTERN RECOGNITION AND ARTIFICIAL INTELLIGENCE 1995年第2期9卷 367-385页

作者： SASTRY, R RANGANATHAN, N UNIV S FLORIDA DEPT COMP SCI & ENGNCTR MICROELECTR RESTAMPAFL 33620

The recognition of polygons in 3-D space is an important task in robot vision. Advances in VLSI technology have now made it possible to implement inexpensive, efficient and very fast custom designs. The authors have earlier proposed a class of VLSI architectures for this computationally intensive task, which makes use of a set of local shape descriptors for polygons which are invariant under affine transformations, i.e. translation, scaling, rotation and orthographic projection from 3-D to any 2-D plane. This paper discusses the design and implementation of PMAC, a prototype for polygon matching, as a custom CMOS VLSI chip. The recognition procedure is based on the matching of edge-length ratios using a simplified version of the dynamic programming procedure commonly employed for string matching. The matching procedure also copes with partial occlusions of polygons. The implemented architecture is systolic and fully utilizes the principles of pipelining and parallelism in order to obtain high speed and throughput.

关键词： PATTERN MATCHING hardware algorithms VLSI IMPLEMENTATION STRING MATCHING TEMPLATE MATCHING SYSTOLIC ARRAY PARALLEL PROCESSING OBJECT RECOGNITION

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Advanced sensors for surveying and mapping

Advanced sensors for surveying and mapping

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Conference on Electro-Optical and Infrared Systems

作者： Eckardt, A Arnold, G Lorenz, E Jahn, H Oertel, D Börner, A DLR German Aerosp Ctr Opt Informat Syst D-12489 Berlin Germany

ISBN: (纸本)0819455652

During the last years the department of Optical Information Systems of the German Aerospace Center (DLR) developed a considerable number of imaging sensor systems for a wide field of applications. Systems with a high geometric and radiometric resolution in dedicated spectral ranges of the electromagnetic spectrum were provided by developing and applying cutting edge technologies. Designed for photogrammetry and remote sensing, such systems play an important role for security and defence tasks. Complete system solutions were implemented considering theoretical framework, hardware design and deployment, overall system tests, calibration, sensor operation and data processing. Outstanding results were achieved with the airborne digital sensor ADS40 and the micro satellite BIRD and its infrared camera payload. Future activities will focus on intelligent cameras and sensor webs. The huge amount of data will force the issue of thematic multi-sensor data processing which is to be implemented in real time near the sensor. In dependence on well defined tasks, combinations of several sensors with special properties will be placed on spaceborne, airbome or terrestrial platforms. The paper gives an overview about finished and current projects and strategic goals.

关键词： photogrammetry remote sensing high resolution real-time application 3D sensors line scanner sensor WEB IR technology micro-satellite hardware algorithms

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FPGA-Based Real-Time Swept-Source OCT Systems for B-Scan Live-Streaming or Volumetric Imaging

FPGA-Based Real-Time Swept-Source OCT Systems for B-Scan Liv...

引用

Conference on Optical Coherence Tomography and Coherence Domain Optical Methods in Biomedicine XVII at the SPIE Photonics West Symposia

作者： Bandi, Vinzenz Goette, Josef Jacomet, Marcel von Niederhaeusern, Tim Bachmann, Adrian H. Duelk, Marcus Bern Univ Appl Sci HuCE MicroLab Bfh Ti CH-2501 Biel Switzerland

ISBN: (纸本)9780819493408

We have developed a Swept-Source Optical Coherence Tomography (Ss-OCT) system with high-speed, real-time signal processing on a commercially available Data-Acquisition (DAQ) board with a Field-Programmable Gate Array (FPGA). The Ss-OCT system simultaneously acquires OCT and k-clock reference signals at 500 MS/s. From the k-clock signal of each A-scan we extract a remap vector for the k-space linearization of the OCT signal. The linear but oversampled interpolation is followed by a 2048-point FFT, additional auxiliary computations, and a data transfer to a host computer for real-time, live-streaming of B-scan or volumetric C-scan OCT visualization. We achieve a 100 kHz A-scan rate by parallelization of our hardware algorithms, which run on standard and affordable, commercially available DAQ boards. Our main development tool for signal analysis as well as for hardware synthesis is MATLAB (R) with add-on toolboxes and 3rd-party tools.

关键词： hardware synthesis hardware algorithms MATLAB/SIMULINK signal processing parallelization OCT B-scan C-scan live-streaming

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A Fast and Scalable FPGA-Based Parallel Processing Architecture for K-Means Clustering for Big Data Analysis

A Fast and Scalable FPGA-Based Parallel Processing Architect...

引用

IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM)

作者： Raghavan, Ramprasad Perera, Darshika G. Univ Colorado Dept Elect & Comp Engn Colorado Springs CO 80933 USA

ISBN: (纸本)9781538607008

The exponential growth of complex, heterogeneous, dynamic, and unbounded data, generated by a variety of fields including health, genomics, physics, climatology, and social networks pose significant challenges in data processing and desired speed-performance. Existing processor-based software-only algorithms are incapable of analyzing and processing this enormous amount of data, efficiently and effectively. Consequently, some kind of hardware support is desirable to overcome the challenges in analyzing big data. Big data analytics involves many important data mining tasks including clustering, which categorizes the data into meaningful groups based on the similarity or dissimilarity among objects. In this research work, we introduce an efficient FPGA-based parallel processing architecture for K-means Clustering, one of the most popular clustering algorithms. Experiments are performed on a benchmark dataset to evaluate the feasibility and efficiency of our hardware design. Our hardware architecture is generic, parameterized, and scalable to support larger and varying datasets as well as a varying number of clusters. Our hardware configuration with 32 processing elements (PEs) achieved 368 times speedup compared to its software counterpart.

关键词： Big data analysis parallel processing architecture FPGAs K-Means clustering embedded hardware hardware algorithms data mining

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MULTIPLICATION AS PARALLEL AS POSSIBLE 1st

MULTIPLICATION AS PARALLEL AS POSSIBLE

引用

1ST INTERNATIONAL CONF ON PARALLEL COMPUTATION

作者： LIPPITSCH, P POSCH, KC POSCH, R GRAZ UNIV TECHNOL DEPT APPL INFORMAT PROC & COMMUN TECHNOLA-8010 GRAZAUSTRIA

ISBN: (纸本)9783540554370

Public key encryption/decryption with modulus arithmetic is used in a variety of cryptographic applications. A tough computational Problem arises due to the very long integer arithmetic needed. Usually serial-parallel multiplication is employed, which slows down speed to the order of k = log2(n), where n is the modulus. This paper describes a possible implementation of a method using parallel multiplication schemes at the order of log(k) in combination with incomplete modulus reduction. As many partial products as possible are implemented in parallel (As Parallel As Possible, APAP). This leads to a mixture of linear and logarithmic time complexity. This paper describes a hardware solution for the APAP-multiplier with optimized dynamic adder cells without storage elements. Additional available silicon area can be traded against speedup in a smooth way. The underlying method is described and proved in [Posch90]. Using 664 bit long operands, a 40mm2 chip manufactured in 1.2 micron CMOS technology can reach an RSA encryption/decryption rate of 240 kbits/second.

关键词： PUBLIC KEY CRYPTOSYSTEMS CRYPTOGRAPHY hardware algorithms VLSI PARALLEL MULTIPLIER HIGH SPEED MULTIPLIER

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