Internet security continues to be a complex and challenging problem. Security mech- anisms such as authentication, data integrity, and data confidentiality along with intrusion detection, intrusion prevention, and fir...
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Internet security continues to be a complex and challenging problem. Security mech- anisms such as authentication, data integrity, and data confidentiality along with intrusion detection, intrusion prevention, and firewall systems have traditionally provided respectable levels of protection. However, malicious actors and their associated attack technologies have advanced significantly. Moreover, Internet-enabled platforms such as cyber-physical infrastructures, advanced mobile voice communication systems, the mobile Internet, voice- over-Internet Protocol (VoIP, cloud computing, the Internet-of-Things, vehicular networks, aerospace networks, intelligent transportation systems, and smart-home environments will provide countless new attack vectors and opportunities for malicious actors. Consequently, advanced security mechanisms and defense methodologies are needed for the continual pro- tection of traditional Internet systems along with these emerging Internet-enabled platforms. However, existing security systems and architectures have a foundation based on the concepts of topological perimeters, non-cooperative and isolated operation, reactive re- configuration, and human advisory. Perimeter-based, isolated, non-cooperative, and ad- ministratively reactive techniques are becoming ineffective, and this is especially true for emergent platforms such as the mobile Internet and cloud computing in which the con- stituent computational and networking resources reside outside of enterprise topologies and perimeters. Isolated and non-cooperative security mechanisms operate within a confined awareness domain, and knowledge related to new security occurrences are not shared out- side of the awareness domain. Isolated is implied by confinement, and non-cooperative is implied by not sharing knowledge with other awareness domains. This imposes a significant impediment in terms of efficient, global-scale Internet security. Lastly, administratively reactive relates to techniques w
Data compression techniques can alleviate bandwidth problems in even multigigabit networks and are especially useful when combined with encryption. This article demonstrates a reconfigurable hardware compressor/decomp...
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Data compression techniques can alleviate bandwidth problems in even multigigabit networks and are especially useful when combined with encryption. This article demonstrates a reconfigurable hardware compressor/decompressor core, the Titan-R, which can compress/decompress data streams at 8.5 Gb/sec, making it the fastest reconfigurable such device ever proposed;the presented full-duplex implementation allows for fully symmetric compression and decompression rates at 8.5 Gbps each. Its compression algorithm is a variation of the most widely used and efficient such scheme, the Lempel-Ziv (LZ) algorithm that uses part of the previous input stream as the dictionary. In order to support this high network throughput, the Titan-R utilizes a very fine-grained pipeline and takes advantage of the high bandwidth provided by the distributed on-chip RAMs of state-of-the-art FPGAs.
A simplified correlation index is proposed to be used in real-time pulse shape recognition systems. This index is similar to the classic Pearson's correlation coefficient, but it can be efficiently implemented in ...
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A simplified correlation index is proposed to be used in real-time pulse shape recognition systems. This index is similar to the classic Pearson's correlation coefficient, but it can be efficiently implemented in FPGA devices with far fewer logic resources and excellent performance. Numerical simulations with synthetic data and comparisons with the Pearson's correlation show the suitability of the proposed index in applications such as the discrimination and counting of pulses with a predefined shape. Superior performance is evident in signal-to-noise ratio scenarios close to unity. FPGA implementation of Person's method and the proposed correlation index have been successfully tested and the main results are summarized.
This paper presents a formal design of arithmetic circuits using an arithmetic description language called ARITH. The key idea in ARITH is to describe arithmetic algorithms directly with high-level mathematical object...
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This paper presents a formal design of arithmetic circuits using an arithmetic description language called ARITH. The key idea in ARITH is to describe arithmetic algorithms directly with high-level mathematical objects (i.e., number representation systems and arithmetic operations/formulae). Using ARITH, we can provide formal description of arithmetic algorithms including those using unconventional number systems. In addition, the described arithmetic algorithms can be formally verified by equivalence checking with formula manipulations. The verified ARITH descriptions are easily translated into the equivalent HDL descriptions. In this paper, we also present an application of ARITH to an arithmetic module generator, which supports a variety of hardware algorithms for 2-operand adders, multi-operand adders, multipliers, constant-coefficient multipliers and multiply accumulators. The language processing system of ARITH incorporated in the generator verifies the correctness of ARITH descriptions in a formal method. As a result, we can obtain highly-reliable arithmetic modules whose functions are completely verified at the algorithm level.
Data compression is the reduction of redundancy in data representation in order to decrease storage and communication costs. Data compression techniques have been used in practice primarily through software implementa...
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Data compression is the reduction of redundancy in data representation in order to decrease storage and communication costs. Data compression techniques have been used in practice primarily through software implementations which do not meet the speed and performance requirements of current and future systems. In this paper we present a new class of efficient hardware algorithms for data compression and decompression that can provide speeds that are an order of magnitude higher than currently obtainable encoding speeds. Our algorithms for the Huffman compression scheme works on the principle of propagation of a token on the reverse binary tree constructed from the original codes. We show how the same principles can be used to develop hardware algorithms to implement the multi-group compression and decompression methods. Finally, a simple circuit that can be used to implement the run-length and header compression methods is described. The algorithms are suitable for VLSI implementation, and data transformation can be done 'on-the-fly'. Based on a prototype VLSI implementation of a compression chip, the algorithms yield an estimated compression rate of 10 M characters per second.
The recognition of patterns is an important task in robot and computer vision. The patterns themselves could be one- or two-dimensional, depending upon the application. Pattern matching is a computationally intensive ...
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The recognition of patterns is an important task in robot and computer vision. The patterns themselves could be one- or two-dimensional, depending upon the application. Pattern matching is a computationally intensive and time consuming operation. The design of special purpose hardware could speed up the matching task considerably, making real-time responses possible. Advances in parallel processing and VLSI technologies have made it possible to implement inexpensive, efficient and very fast custom designs. Many approaches and solutions have been proposed in the literature for hardware implementations of pattern matching techniques. In this paper, we present a detailed overview of some of the important contributions in the area of hardware algorithms and architectures for pattern matching.
As mobile and handheld devices are gaining popularity, many applications have found their ways into these devices. In order to use these mobile systems effectively and efficiently, it is important to optimize their em...
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ISBN:
(纸本)9781479915002
As mobile and handheld devices are gaining popularity, many applications have found their ways into these devices. In order to use these mobile systems effectively and efficiently, it is important to optimize their embedded software and hardware. This work focuses on hardware support for mobile and embedded applications in single-chip format so as to reduce the hardware footprint as required in these handheld devices. Applications specific circuits, single-core microprocessor, and field programmable gate arrays are presented, and their strengths and weaknesses are discussed. Reconfigurable computing systems, specifically FPGA-based approaches, are introduced, and techniques for their reconfiguration are analyzed. It is concluded that reconfigurable FPGA-based system is currently the best option to deliver embedded applications that have stringent requirements.
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