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hardware complexity of modular multiplication and exponentiation

IEEE TRANSACTIONS ON COMPUTERS 2007年第10期56卷 1308-1319页

作者： David, Jean Pierre Kalach, Kassem Tittley, Nicolas Univ Montreal Dept Informat & Rech Operat Montreal PQ H3C 3A7 Canada Ecole Polytech Genie Elect Montreal PQ H3C 3A7 Canada Catholic Univ Louvain DICE Crypto Grp B-1348 Louvain Belgium

Large integer Modular Multiplication (MM) and Modular Exponentiation (ME) are the foundation of most public-key cryptosystems, specifically RSA, Diffie-Helleman, ElGamal, and the Elliptic Curve Cryptosystems. Thus, MM algorithms have been studied widely and extensively. Most of the work is based on the well-known Montgomery Multiplication Method and its variants, which require standard multiplication operations. Despite their better complexity orders, Karatsuba and FFT algorithms seem to rarely be used for hardware implementation. In this paper, we review their hardware complexity and propose original implementations of MM and ME that become useful for 24-bit operators (Karatsuba algorithm) or 373-bit operators (FFT algorithm).

关键词： cryptography multiplication modular arithmetic hardware complexity

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hardware complexity of SHA-1 and SHA-256 based on area and time analysis

Hardware complexity of SHA-1 and SHA-256 based on area and t...

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26th International Conference on Information Networking 2012, ICOIN 2012

作者： Jeon, Jun-Cheol Seo, Kang-Joong Kim, Kee-Won Dept. of Information Security Woosuk University Jeonbuk Korea Republic of

ISBN: (纸本)9781467302517

This paper presents the analysis of a gate-level hardware complexity of SHA-1 and SHA-256. There are several kinds of SHA series' analysis on a hardware point of view but their analyses can be relatively measured according to the given equipments and facilities. In this paper, we provide a logical approach on hardware complexity analysis in area and time angle defined by the number of transistors needed for its construction and the time needed for the signal change to propagate through gates. © 2012 IEEE.

关键词： Area and time complexity hardware complexity SHA-1 SHA-256 Secure Hashing Algorithm Computer hardware

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A fractional filter-based beamformer architecture using postfiltering approach to minimize hardware complexity

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IEEE TRANSACTIONS ON ULTRASONICS FERROELECTRICS AND FREQUENCY CONTROL 2007年第5期54卷 1076-1079页

作者： Cho, Jeong Lee, Jun-Young Song, Jac-Hee Kim, Younglok Song, Tai-Kyong Sogang Univ Dept Elect Engn Seoul South Korea

A novel beamformer architecture using fractional delay filters is proposed and verified through experiments. By performing interchannel summation prior to filtering operation in the manner producing no error, the proposed architecture requires only three four-tap filters for the whole beamformer and four simple demultiplexers per each channel.

关键词： demultiplexing equipment optical design techniques optical filters beamformer demultiplexers four-tap filters fractional delay filters hardware complexity postfiltering

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Comparison of hardware complexity between convolutional guided scrambling and Galois-field-addition guided scrambling for digital recording

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Kyokai Joho Imeji Zasshi/Journal of the Institute of Image Information and Television Engineers 2000年第7期54卷 1079-1088页

作者： Kunisa, Akiomi Hypermedia Research Center SANYO Electric Co. Ltd. 3-10-15 Hongo Bunkyo-ku Tokyo 113-8434 Japan

The guided scrambling (GS) coding technique is used to control the runlength within code blocks, such as d or k, as well as to suppress the DC component. It achieves a code rate very close to the channel capacity. In a GS encoder, a selection set of channel bit streams is constructed by subjecting a source bit stream to several kinds of scramblings and to runlength limited (RLL) coding if necessary. Then one that satisfies the imposed channel constraints best is selected. Typically, the GS technique uses a convolutional operation or an addition operation in the Galois field (GF);these two schemes can generate channel bit streams that meet the channel constraints better than conventional coding techniques. The latter scheme is better in terms of symbol-error probability when both schemes are concatenated with Reed-Solomon (RS) codes. However, nothing is known about the hardware complexity of either scheme. We describe their hardware configurations using ROM tables and compare the table sizes. From this comparison, we conclude that the hardware complexity of the latter scheme is smaller under certain conditions.

关键词： digital recording guided scrambling runlength limited DC-free hardware complexity

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Downlink Precoding Design for Full-Duplex Enabled Massive MIMO Systems with Low hardware complexity 9

Downlink Precoding Design for Full-Duplex Enabled Massive MI...

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9th International Symposium on Telecommunications (IST)

作者： Omid, Yasaman Shahabi, Seyyed MohammadMahdi Ardebilipour, Mehrdad KN Toosi Univ Technol Dept Elect Engn Tehran Iran

ISBN: (纸本)9781538682746

This paper aims to design a downlink precoding scheme for the base stations (BS) by concentration on both hardware complexity and interference mitigation capability in a cellular multi-user massive multiple input multiple output (MIMO) full-duplex (FD) enabled system. The presented precoder makes an effort to mitigate the power of three interference terms: the self-interference (SI) in the uplink, the multi-user interference in the downlink and the BS-to-BS interference of the uplink transmission. To reduce the implementation costs, a low hardware complexity (LHC) precoding design is utilized in which only a single radio frequency (RF) amplifier is required in each BS. However, since this structure requires full cellular collaboration, to reinforce the performance from the overhead point of view, a LHC precoding with small inter-cell collaboration is proposed. The precoding design is extended to a case where the channel state information (CSI) is imperfect due to pilot contamination, and it is attempted to combat this effect. Numerical results demonstrate the out-performance of the LHC schemes compared to the prior zero-forcing (ZF) based methods in the literature both in the uplink and in the downlink. The promising performance of the LHC-based pilot contamination cancellation design is also depicted in case imperfect CSI is at hand. Furthermore, it is shown that the overhead reduction is achieved with a minor performance degradation, which seems to be worth the cost.

关键词： Massive MIMO Full Duplex Pilot Contamination hardware complexity

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FMCW LiDAR System to Reduce hardware complexity and Post-Processing Techniques to Improve Distance Resolution

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SENSORS 2020年第22期20卷 6676.-6676.页

作者： Kim, Chankyu Jung, Yunho Lee, Seongjoo Sejong Univ Dept Informat & Commun Engn Seoul 05006 South Korea Korea Aerosp Univ Sch Elect & Informat Engn Goyang Si 10540 South Korea

As the autonomous driving technology develops, research on related sensors is also being actively conducted. One system that is widely used today uses a light source with a wavelength in the 905 nm band for the pulse Light Detection And Ranging (LiDAR) system. This has the disadvantages of being harmful to the human eye and in making digital signal processing difficult at high sampling rates. The Frequency Modulated Continuous Wave (FMCW) LiDAR system has been proposed as an alternative. However, the FMCW LiDAR is formed with a high beat frequency by a method different from that of the FMCW Radar, which causes a hardware burden on the FFT (Fast Fourier Transform) module for interpreting the beat frequency information. In this paper, the FFT module that may occur in the FMCW LiDAR using Digital Down Convert (DDC) technology is extracted at 256 points, which is 25 times smaller than the existing 8192 points, and the beat frequency is 0 to 50 m at 3 cm intervals. As a result of generating and restoring the distance, the performance of 0.03 m Root Mean Square Error (RMSE) compared to the conventional one was confirmed. In this process, the hardware module was directly mounted and verified on the FPGA. In the case of the Simple Threshold-Constant False Alarm Rate (ST-CFAR) provided, the RMSE was measured by generating beat frequencies from 0 to 50 m at 1 cm intervals, and as a result, the result of 0.019 m was confirmed at 0.03 m in the past.

关键词： FMCW LiDAR FFT hardware complexity FPGA FMCW LiDAR Digital Down Convert

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Performance and hardware complexity Tradeoffs in Designing Multithreaded Architectures 96

Performance and Hardware Complexity Tradeoffs in Designing M...

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Proceedings of the 1996 Conference on Parallel Architectures and Compilation Techniques

作者： Michael Bekerman Avi Mendelson Gad Sheaffer

This paper presents performance and step-by-step complexity analysis of two different design alternatives of multithreaded architecture: dynamic inter-thread resource scheduling and static resource allocation. We show that with two concurrent threads the dynamic scheduling processor achieves from 5 to 45% higher performance at the cost of much more complicated design. The paper shows that for a relatively high number of execution resources the complexity of the dynamic scheduling logic will inevitably require design compromises. Moreover, high chip-wide communication time and an "incomplete bypassing network" will force the dynamic scheduling to use static-like execution unit assignment, thus reducing its performance advantage. At the same transistor budget the static architecture may implement additional functional units, resulting in better overall performance.

关键词： hardware complexity performance evaluation ILP multithreaded architecture

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Low-complexity Photonic Wireless Channel Estimation System Based on Matrix- Condition-Number Theory

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IEEE PHOTONICS TECHNOLOGY LETTERS 2025年第6期37卷 333-336页

作者： Yu, Zhiyi Zhao, Yang Li, Zhiting Xu, Shaofu Zou, Weiwen Shanghai Jiao Tong Univ Intelligent Microwave Lightwave Integrat Innovat C Dept Elect Engn State Key Lab Adv Opt Commun Syst & Networks Shanghai 200240 Peoples R China

We propose a photonic channel estimation architecture for wireless communication systems with reduced hardware complexity. This work can achieve high-accuracy channel estimation with low cost, solving the problem of existing architecture being too complicated to be practically deployed. Using matrix-condition-number theory, we derived a simplified method to conduct Fourier matrix. hardware complexity is therefore reduced by tens to hundreds times in OFDM systems. The proof-of-concept experiment was conducted in an OFDM system with 8 channel paths, which contains 128/256/512 subcarriers, respectively. Experimental results show that the mean square errors between the experimental channel state information and practical channel state information lie on the order of 10-4. And the bit error rate is obviously below the forward error correction threshold, satisfying the requirements of OFDM wireless communication.

关键词： OFDM wireless communication hardware complexity hardware complexity Photonic channel estimation OFDM wireless communication hardware complexity

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Design of IP optical nodes based on AWG with shared tunable wavelength converters

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OPTICAL SWITCHING AND NETWORKING 2011年第1期8卷 23-31页

作者： Bregni, Stefano Pattavina, Achille Rebughini, Marica Sipone, Antonio Politecn Milan Dept Elect & Informat I-20133 Milan Italy

In order to meet the ever-growing demand of transmission capacity, optical packet switching technology is emerging as a major candidate, promising to allow fast dynamic allocation of WDM channels, combined with a high degree of statistical resource sharing. This paper describes the architecture of an optical switching node for IF networks based on an arrayed waveguide grating device to route packets. Given the high cost of optical components needed to route packets inside the AWG, two node architectures equipped with a pool of tunable wavelength converters fully shared among all input ports are proposed. Here an analytical model is developed that allows us to evaluate the performance of a bufferless optical switch architecture. Computer simulation is used as well to evaluate the packet loss probability in the node under various buffering arrangements by comparing different scheduling algorithms. (C) 2010 Elsevier B.V. All rights reserved.

关键词： Optical packet switching Arrayed waveguide grating (AWG) Tunable wavelength converter (TWC) WDM network hardware complexity IP protocol Traffic performance

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Precoding in downlink multi-carrier code division multiple access systems using expectation maximisation algorithm

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IET COMMUNICATIONS 2008年第10期2卷 1279-1288页

作者： Haghbin, A. Azmi, P. Tarbiat Modares Univ Dept Elect Engn Tehran Iran

The presence of multiple access interference and hardware complexity of the mobile terminal are two major burdens for multi-carrier code division multiple access schemes. Both burdens can be overcome in downlink by precoding the transmitted signal using the knowledge of the channel state information. In multi-user precoding techniques, the transmitter is optimised to combat channel impairments through the use of new spreading sequences that are obtained by solving an optimisation problem based on some criterion. Among these optimisation problems, the problem based on maximum likelihood is hard and complex to solve. In the proposed precoding scheme, the well-suited expectation maximisation algorithm is used to solve this problem. The proposed precoding technique is simulated and its performance is analysed and compared with some other precoding and detecting techniques. The results show that the proposed scheme considerably outperforms the previous precoding schemes.

关键词： multiuser precoding techniques maximum likelihood decoding multiple access interference mobile terminal code division multiple access hardware complexity radiofrequency interference expectation maximisation algorithm optimisation problem precoding mobile radio expectation-maximisation algorithm channel state information downlink multicarrier code division multiple access systems multiuser channels

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