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Cost-effective triple-mode reconfigurable pipeline FFT/IFFT/2-D DCT processor

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2008年第8期16卷 1058-1071页

作者： Lin, Chin-Teng Yu, Yuan-Chu Van, Lan-Da Natl Chiao Tung Univ Coll Elect Engn & Comp Sci Hsinchu 300 Taiwan Natl Chiao Tung Univ Dept Comp Sci Hsinchu 300 Taiwan Natl Chiao Tung Univ Dept Elect & Control Engn Hsinchu 300 Taiwan

This investigation proposes a novel radix-4(2) algorithm with the low computational complexity of a radix-16 algorithm but the lower hardware requirement of a radix-4 algorithm. The proposed pipeline radix-4(2) single delay feedback path (R4(2)SDF) architecture adopts a multiplierless radix-4 butterfly structure, based on the specific linear mapping of common factor algorithm (CFA), to support both 256-point fast Fourier transform/inverse fast Fourier transform (FFT/IFFT) and 8 x 8 2-D discrete cosine transform (DCT) modes following with the high efficient feedback shift registers architecture. The segment shift register (SSR) and overturn shift register (OSR) structure are adopted to minimize the register cost for the input re-ordering and post computation operations in the 8 x 8 2-D DCT mode, respectively. Moreover, the retrenched constant multiplier and eight-folded complex multiplier structures are adopted to decrease the multiplier cost and the coefficient ROM size with the complex conjugate symmetry rule and subexpression elimination technology. To further decrease the chip cost, a finite wordlength analysis is provided to indicate that the proposed architecture only requires a 13-bit internal wordlength to achieve 40-dB signal-to-noise ratio (SNR) performance in 256-point FFT/IFFT modes and high digital video (DV) compression quality in 8 x 8 2-D DCT mode. The comprehensive comparison results indicate that the proposed cost effective reconfigurable design has the smallest hardware requirement and largest hardware utilization among the tested architectures for the FFT/IFFT computation, and thus has the highest cost efficiency. The derivation and chip implementation results show that the proposed pipeline 256-point FFT/IFFT/2-D DCT triple-mode chip consumes 22.37 mW at 100 MHz at 1.2-V supply voltage in TSMC 0.13-mu m CMOS process, which is very appropriate for the RSoCs IP of next-generation handheld devices.

关键词： computation complexity cost effective hardware utilization next-generation wireless communications pipeline architecture R4(2)SDF triple modes

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ELIMINATING INTERLOCKS IN DEEPLY PIPELINED PROCESSORS BY DELAY ENFORCED MULTISTREAMING

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IEEE TRANSACTIONS ON COMPUTERS 1991年第10期40卷 1125-1132页

作者： MCCRACKIN, DC Department of Electrical and Computer Engineering McMaster University Hamilton ONT Canada

The delay enforced multistreaming (DEMUS) processor architecture provides a simple, inexpensive way of achieving high hardware utilization in deeply pipelined processors. Multiple streams share the pipeline in an interleaved fashion. Both the data dependency problem and the jump problem are prevented by enforcing enough interdispatch delay on each individual stream to prevent successive instructions from interfering with each other's execution. The structure and operation of a small DEMUS processor are presented, and several stream dispatching algorithms are compared by means of a simple simulation.

关键词： EFFICIENT CONTROL hardware utilization MIMD COMPUTERS PIPELINE INTERLOCKS SIMULATION STREAM INTERLEAVING

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Multithreading with distributed functional units

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IEEE TRANSACTIONS ON COMPUTERS 1997年第4期46卷 399-411页

作者： Gunther, BK Advanced Computing Research Centre School of Computer and Information Science University of South Australia Adelaide Australia

Multithreaded processors multiplex the execution of a number of concurrent threads onto the hardware in order to hide latencies associated with memory access, synchronization, and arithmetic operations. Conventional multithreading aims to maximize throughput in a single instruction pipeline whose execution stages are served by a collection of centralized functional units. This paper examines a multithreaded microarchitecture where the heterogeneous functional unit set is expanded so that units may be distributed and partly shared across several instruction pipelines operating simultaneously, thereby allowing greater exploitation of interthread parallelism in improving utilization factors of costly resources. The multiple pipeline approach is studied specifically in the Concurro processor architecture-a machine supporting multiple thread contexts and capable of context switching asynchronously in response to dynamic data and resource availability. Detailed simulations of Concurro processors indicate that instruction throughputs for programs accessing main memory directly can be scaled, without recompilation, from one to over eight instructions per cycle simply by varying the number of pipelines and functional units. In comparison with an equivalent coherent-cache, single-chip multiprocessor, Concurro offers marginally better performance at less than half of the estimated implementation cost. With suitable prefetching, multiple instruction caches can be avoided, and multithreading is shown to obviate the need for sophisticated instruction dispatch mechanisms on parallel workloads. Distribution of functional units results in a 150% improvement over the centralized approach in utilization factors of arithmetic units, and enables saturation of the most critical processor resources.

关键词： distributed functional units hardware utilization latency tolerance multiple context processors multithreading pipelined computers pre-access instruction cache simulation synchronization

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Low area FPGA implementation of PRESENT cryptography with 3S-RLKG and MKS

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WIRELESS NETWORKS 2021年第8期27卷 5397-5416页

作者： Tappari, Sunitha G Narayanamma Inst Technol & Sci Dept Elect & Telemat Engn Hyderabad India

Nowadays, security and confidentiality are considered as important aspects throughout the growth of computerized systems, information technology, and internet communication. The cryptographic algorithms are used to improve the security against various threats/attacks (e.g., differential attacks and statistical attacks). In this research, the modified PRESENT architecture is proposed to improve the security against unauthorized users while minimizing the hardware utilization. The PRESENT architecture is modified by proposing three key strategies;(1) three Stage Reversible Logic Key Generation (3S-RLKG) is developed to generate the optimal key value using three different gates such as Feynman gate, DFG gate and Toffoli gate, (2) Modified Key Scheduling (MKS) and Bit Reversible Function (BRF) is additionally used in the PRESENT architecture to increase the confusion property and (3) mitigation of the Read-Only Memory (ROM) to store the intermediate values in the Field Programmable Gate Array (FPGA) processor. Therefore, the higher confusion property leads to an increase in the security against the unauthorized users. The performance of 3S-RLKG-PRESENT architecture is evaluated by means of the number of slice registers, flip flops, number of Look Up Table (LUT), number of logical elements, slices and bonded input/output block (IOB). Moreover, the 3S-RLKG-PRESENT architecture is also analyzed in the Spartan 6 XC6SLX9 -2 TQG144 FPGA hardware. The 3S-RLKG-PRESENT architecture is compared with different existing PRESENT architectures namely Maximum Distance Separable (MDS) based PRESENT, PRESENT, PRESENT with X Compactor, PRESENT- Round Key Generation (RKG), PRESENT- Storage Mode (SM) and Pseudo Random Bit Generator (PRBG). The 3S-RLKG-PRESENT designed in the Spartan 6 consumes 131 LUTs, 70 flip flops and 48 slices which are less when compared to the PRESENT-RKG.

关键词： hardware utilization Lightweight cryptography PRESENT block cipher Pseudo-random number generator True random number generator

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Low Area PRESENT Cryptography in FPGA Using TRNG-PRNG Key Generation

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Computers, Materials & Continua 2021年第8期68卷 1447-1465页

作者： T.Kowsalya R.Ganesh Babu B.D.Parameshachari Anand Nayyar Raja Majid Mehmood Department of Electronic and Communication Engineering Muthayammal Engineering CollegeRasipuramNamakkalTamilnaduIndia Department of Electronics and Communication Engineering SRM TRP Engineering CollegeTiruchirappalliTamilnaduIndia Department of Telecommunication Engineering GSSS Institute of Engineering and Technology for WomenMysuruIndia Faculty of Information Technology Graduate SchoolDuy Tan UniversityDa Nang550000Viet Nam Department of Information and Communication Technology School of Electrical and Computer EngineeringXiamen University MalaysiaSepang43900Malaysia

Lightweight Cryptography(LWC)is widely used to provide integrity,secrecy and authentication for the sensitive ***,the LWC is vulnerable to various constraints such as high-power consumption,time consumption,and hardware utilization and susceptible to the malicious *** order to overcome this,a lightweight block cipher namely PRESENT architecture is proposed to provide the security against malicious *** True Random Number Generator-Pseudo Random Number Generator(TRNG-PRNG)based key generation is proposed to generate the unpredictable keys,being highly difficult to predict by the ***,the hardware utilization of PRESENT architecture is optimized using the Dual port Read Only Memory(DROM).The proposed PRESENT-TRNGPRNG architecture supports the 64-bit input with 80-bit of key *** performance of the PRESENT-TRNG-PRNG architecture is evaluated by means of number of slice registers,flip flops,number of slices Look Up Table(LUT),number of logical elements,slices,bonded input/output block(IOB),frequency,power and *** input retrieval performances analyzed in this PRESENT-TRNG-PRNG architecture are Peak Signal to Noise Ratio(PSNR),Structural Similarity Index(SSIM)and Mean-Square Error(MSE).The PRESENT-TRNG-PRNG architecture is compared with three different existing PRESENT architectures such as PRESENT On-TheFly(PERSENT-OTF),PRESENT Self-Test Structure(PRESENT-STS)and PRESENT-Round Keys(PRESENT-RK).The operating frequency of the PRESENT-TRNG-PRNG is 612.208 MHz for Virtex 5,which is high as compared to the PRESENT-RK.

关键词： Dual port read only memory hardware utilization lightweight cryptography malicious attackers present block cipher pseudo random number generator true random number generator

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FPGACam: A FPGA based efficient camera interfacing architecture for real time video processing

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IET CIRCUITS DEVICES & SYSTEMS 2021年第8期15卷 814-829页

作者： Sarkar, Sayantam Bhairannawar, Satish S. K. B., Raja Vijaya Vittala Inst Technol Dept Elect & Commun Engn Bangalore 560077 Karnataka India Shri Dharmasthala Manjunatheshwara Coll Engn & Te Dept Elect & Commun Engn Dharwad Karnataka India Univ Visvesvaraya Dept Elect & Commun Engn Coll Engn Bangalore Karnataka India

In most of the real time video processing applications, cameras are used to capture live video with embedded systems/Field Programmable Gate Arrays (FPGAs) to process and convert it into the suitable format supported by display devices. In such cases, the interface between the camera and display device plays a vital role with respect to the quality of the captured and displayed video, respectively. In this paper, we propose an efficient FPGA-based low cost Complementary Metal Oxide Semiconductor (CMOS) camera interfacing architecture for live video streaming and processing applications. The novelty of our work is the design of optimised architectures for Controllers, Converters, and several interfacing blocks to extract and process the video frames in real time efficiently. The flexibility of parallelism has been exploited in the design for Image Capture and Video Graphics Array (VGA) Generator blocks. The Display Data Channel Conversion block required for VGA to High Definition Multimedia Interface Conversion has been modified to suit our objective by using optimised Finite State Machine and Transition Minimiszed Differential Signalling Encoder through the use of simple logic architectures, respectively. The hardware utilization of the entire architecture is compared with the existing one which shows that the proposed architecture requires nearly 44% less hardware resources than the existing one.

关键词： video frames video streaming display devices interfacing blocks captured displayed video optimised architectures hardware utilization hardware resources video graphics array generator blocks entire architecture display device video signal processing finite state machines live video streaming complementary metal oxide semiconductor camera high definition multimedia interface conversion multimedia communication FPGA based efficient camera interfacing architecture display data channel conversion block simple logic architectures FPGACam optimised finite state machine real time video processing applications embedded systems field programmable gate arrays transition minimiszed differential signalling encoder image capture cameras

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An efficient implementation of novel Paillier encryption with polar encoder for 5G systems in VLSI

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COMPUTERS & ELECTRICAL ENGINEERING 2018年 65卷 153-164页

作者： Ganesan, Indumathi Balasubramanian, Aarthi Alias Ananthakirupa Muthusamy, Ramesh Mepco Schlenk Engn Coll ECE Sivakasi Tamil Nadu India Mepco Schlenk Engn Coll Sivakasi Tamil Nadu India Kamaraj Coll Engn & Technol Elect & Commun Engn Virudunagar Tamil Nadu India

In this paper, a novel design of Paillier encryption with a modified polar encoding is proposed and analyzed. A new cross-partitioned add shift processing element based on perfect reconstruction technique is designed for the realization of encryption with proper distribution of adders and shifters to minimize the logical component and register usage. In addition, a modified architecture for the polar encoder with optimal delay/minimized hardware resource is achieved by presenting a novel delay calculation methodology followed by register allocation grouped as the Reduced Register Delay Allocation (RRDA) algorithm. Resource utilization, including slice registers, lookuptables (LUTs) and DSP blocks are measured along with operating speed and throughput for the proposed paillier encryption and polar encoder. Finally, the performance is analyzed with the existing designs. The proposed sequential encoding-encryption can be deployed in imminent 5G systems. (C) 2017 Elsevier Ltd. All rights reserved.

关键词： Paillier encryption Polar encoder Field programmable gate array hardware utilization 5G

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VLSI implementation of an energy-efficient color image compressor using improved block truncation coding and enhanced Golomb-rice coding for wireless sensor networks

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JOURNAL OF SUPERCOMPUTING 2024年第17期80卷 24807-24834页

作者： Nirmala, R. Begum, S. Ariffa Selvanayagi, A. Ramya, P. Vivekanandha Coll Engn Women Autonomous ECE Tiruchengode India Kalasalingam Acad Res & Educ Sch Comp CSE Krishnan Koil Tamil Nadu India M Kumarasamy Coll Engn CSE Karur Tamil Nadu India Bannari Amman Inst Technol ECE Sathyamangalam Tamil Nadu India

The very large-scale integration implementation of a unique hardware-oriented image compression technique for wireless sensor networks (WSNs) is presented in this work. Networks of individually owned sensors spread out throughout an area that can detect, measure, and report changes in environmental variables are known as wireless sensor networks (WSNs). Color sampling, block truncation coding (BTC), threshold optimization, sub-sampling, estimation, quantization, and enhanced Golomb-rice coding (EGRC) are all included in the proposed design. A unique improved BTC with an enhanced Golomb-rice coding (IBTC-EGRC) framework has been proposed in this paper. IBTC training framework has been developed using the fuzzy decision-based approach to achieve representative levels and satisfy WSN requirements to accomplish the cost-effective and power-efficient features. Two ideal reconstruction values and bitmap files have been obtained for every block. IBTC divides images into variable block sizes for mathematical translation and inter-pixel redundancy removal. The subsampling, estimation, and quantization stages have minimized redundant data. Finally, EGRC has been used to code the value with the highest likelihood. An EGRC module decreases memory use and computation complexity. The EGRC technique reduces hardware resource utilization by removing the need for the context module, a crucial part of lossless image compressor designs and its memory. Proposed method, Golomb-rice parameter forecasting and managment module is used to preserve pixel connection and improved compression ratio. A UMC 180 nm CMOS technology has been used to implement the suggested framework. This design has 5.8k synthesized gate counts and a core area of 56,000 mu m2. 100 MHz and 3.01 mW were the operational frequency and energy consumption, respectively. The proposed method has a 9.37% reduction in gate count compared to the previous fuzzy BTC-based approach.

关键词： Image compressor VLSI Enhanced Golomb-rice coding WSN Block truncation coding Fuzzy Energy efficiency Compression ratio hardware utilization

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An Automated Resource Management System to Improve Production Tapeout Turn-Around Time

An Automated Resource Management System to Improve Productio...

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Conference on Design for Manufacturability through Design-Process Integration VII

作者： Guo, Eric Liu, Qingwei Zhu, Sherry Wu, Jason Tsai, Jenny Lu, Junwei Simmons, Mark C. Semiconductor Manufacturing International Corp. (China) Mentor Graphics Corp. (United States) Mentor Graphics Corp. (China)

ISBN: (纸本)9780819494665

In today's semiconductor industry, both the pure-play and independent device manufacturer (IDM) foundries are constantly and rigorously competing for market share. The acknowledged benefit for customers who partner with these foundries includes a reduced cost-of-ownership, along with the underwritten agreement of meeting or exceeding an aggressive time-to-market schedule. Because the Semiconductor Manufacturing International Corporation (SMIC) is one of the world-wide forerunners in the foundry industry, one of its primary concerns is ensuring continual improvement in its fab's turnaround time (TAT), especially given that newer technology nodes and their associated processes are increasing in complexity, and consequently, in their time-to-process. In assessing current runtime data trends at the 65nm and 40nm technology nodes, it was hypothesized that hardware and software utilization improvements could accomplish a reduced overall TAT. By running an experiment using the Mentor Graphics Calibre (R) Cluster Manager (CalCM) software, SMIC was able to demonstrate just over a 30% aggregate TAT improvement in conjunction with a greater than 90% average utilization of all hardware resources. This paper describes the experimental setup and procedures that predicated the reported results. Keywords: semiconductor, foundry,

关键词： semiconductor foundry turnaround time cluster manager hardware utilization post tape-out flow mask data prep

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An Efficient Turbo Receiver for LTE Downlink

An Efficient Turbo Receiver for LTE Downlink

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International Conference on Wireless Communications and Signal Processing (WCSP)

作者： Wang, Ying Jiang, Ming Zhao, Chunming Southeast Univ Natl Mobile Commun Res Lab Nanjing Jiangsu Peoples R China

ISBN: (纸本)9781479903085

In this paper, we proposed an efficient shuffled-turbo receiver for the downlink transmission in the long term evolution (LTE) systems. Different with the conventional ones, all modules in the shuffled-turbo receiver work simultaneously. Improved hardware utilization and processing efficiency are achieved owing to this workflow. Besides, our receiver can adaptively support various scenarios with flexible bandwidth configurations. Simulation results show that with preset processing latency in the LTE downlink system, the proposed shuffled-turbo receiver can achieve better performance than the conventional MMSE-ISDIC iterative receiver since the shuffled one can complete more outer-iterations.

关键词： shuffled-turbo receiver LTE downlink iterative receiver processing latency hardware utilization

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