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49th IEEE International conference on Acoustics, Speech, and Signal Processing (ICASSP)

作者： Abdullah-Al Kaiser, Md Jaiswal, Akhilesh R. Univ Southern Calif Elect & Comp Engn Los Angeles CA 90007 USA Univ Wisconsin Madison Elect & Comp Engn Madison WI USA

ISBN: (纸本)9798350344868;9798350344851

The high volume of data transmission between the edge sensor and the cloud processor leads to energy and throughput bottlenecks for resource-constrained edge devices focused on computer vision. Hence, researchers are investigating different approaches (e.g., near-sensor processing, in-sensor processing, in-pixel processing) by executing computations closer to the sensor to reduce the transmission bandwidth. Specifically, in-pixel processing for neuromorphic vision sensors (e.g., dynamic vision sensors (DVS)) involves incorporating asynchronous multiply-accumulate (MAC) operations within the pixel array, resulting in improved energy efficiency. In a CMOS implementation, low overhead energy-efficient analog MAC accumulates charges on a passive capacitor;however, the capacitor's limited charge retention time affects the algorithmic integration time choices, impacting the algorithmic accuracy, bandwidth, energy, and training efficiency. consequently, this results in a design trade-off on the hardware aspect-creating a need for a low-leakage compute unit while maintaining the area and energy benefits. In this work, we present a holistic analysis of the hardware-algorithm co-design trade-off based on the limited integration time posed by the hardware and techniques to improve the leakage performance of the in-pixel analog MAC operations.

关键词： Neuromorphic Vision Sensors convolution In-pixel Processing hardware-algorithm co-design DVS128-Gesture

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OPT-GCN: A Unified and Scalable Chiplet-Based Accelerator for High-Performance and Energy-Efficient GCN computation

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IEEE TRANSACTIONS ON coMPUTER-AIDED design OF INTEGRATED CIRCUITS AND SYSTEMS 2024年第12期43卷 4827-4840页

作者： Zhao, Yingnan Wang, Ke Louri, Ahmed George Washington Univ Dept Elect & Comp Engn Washington DC 20052 USA Univ North Carolina Charlotte Dept Elect & Comp Engn Charlotte NC 28223 USA

As the size of real-world graphs continues to grow at an exponential rate, performing the graph convolutional network (GCN) inference efficiently is becoming increasingly challenging. Prior works that employ a unified computing engine with a predefined computation order lack the necessary flexibility and scalability to handle diverse input graph datasets. In this article, we introduce OPT-GCN, a chiplet-based accelerator design that performs GCN inference efficiently while providing flexibility and scalability through an architecture-algorithm co-design. On the architecture side, the proposed design integrates a unified computing engine in each chiplet and an active interposer, both of which are adaptable to efficiently perform the GCN inference and facilitate data communication. On the algorithm side, we propose dynamic scheduling and mapping algorithms to optimize memory access and on-chip computations for diverse GCN applications. Experimental results show that the proposed design provides a memory access reduction by a factor of 11.3x, 3.4x, and 1.4x, and energy savings of 15.2x, 3.7x, and 1.6x on average compared to HyGCN, AWB-GCN, and GCNAX, respectively.

关键词： Engines System-on-chip Vectors Inference algorithms computer architecture Energy efficiency design automation Chiplet-based design graph convolutional network (GCN) hardware accelerator hardware-algorithm co-design

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design of Novel Analog compute Paradigms with Ark 24

Design of Novel Analog Compute Paradigms with Ark

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29th ACM International conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)

作者： Wang, Yu-Neng cowan, Glenn Ruehrmair, Ulrich Achour, Sara Stanford Univ Stanford CA 94305 USA Concordia Univ Montreal PQ Canada TU Berlin Berlin Germany Univ Connecticut Storrs CT USA

ISBN: (纸本)9798400703850

Previous efforts on reconfigurable analog circuits mostly focused on specialized analog circuits, produced through careful co-design, or on highly reconfigurable, but relatively resource inefficient, accelerators that implement analog compute paradigms. This work deals with an intermediate point in the design space: specialized reconfigurable circuits for analog compute paradigms. This class of circuits requires new methodologies for performing co-design, as prior techniques are typically highly specialized to conventional circuit classes (e.g., filters, ADCs). In this context, we present Ark, a programming language for describing analog compute paradigms. Ark enables progressive incorporation of analog behaviors into computations, and deploys a validator and dynamical system compiler for verifying and simulating computations. We use Ark to codify the design space for three different exemplary circuit design problems, and demonstrate that Ark helps exploring design trade-offs and evaluating the impact of non-idealities to the computation.

关键词： analog computing unconventional computing paradigms hardware-algorithm co-design

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A Multi-scale Block PatchMatch-based Unified algorithm for Efficient 6-D Vision Processing

A Multi-scale Block PatchMatch-based Unified Algorithm for E...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Wang, Hongyu Zhang, Xiangyu Lou, Xin ShanghaiTech Univ Sch Informat Sci & Technol Shanghai Peoples R China Minist Educ Key Lab Intelligent Percept & Human Machine Colla Shanghai Peoples R China

ISBN: (纸本)9798350330991;9798350331004

6-D vision, which combines stereo and flow estimation to derive 3-D location and motion information, is crucial for comprehensive real-world perception. This paper presents a multi-scale block PatchMatch (MBPM)-based efficient 6-D vision algorithm with a balance tradeoff between computational complexity and accuracy, making it suitable for embedded application scenarios. By adopting a random search strategy, the proposed algorithm effectively reduces the computational burden without compromising accuracy. Additionally, the block-level processing approach further enhances efficiency by processing data in smaller, manageable chunks. Due to the significantly larger search range in flow estimation compared to stereo, we further incorporate direction initialization and multi-scale PatchMatch propagation techniques. These enhancements are crucial for ensuring reliable accuracy while expediting algorithm convergence. compared with existing 6-D vision algorithms, the proposed method achieves 16.7% higher accuracy in stereo and 11.1% in flow estimation with much lower complexity. Even when faced with larger searching ranges, the proposed method exhibits consistent accuracy, allowing it to effectively handle fast motion scenarios.

关键词： 6-D vision optical flow stereo matching low complexity hardware-algorithm co-design

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A 1024-Neuron 1M-Synapse Event-Driven SNN Accelerator for DVS Applications

A 1024-Neuron 1M-Synapse Event-Driven SNN Accelerator for DV...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Cheng, Xi Cao, Shu Wang, Shangmei Zeng, Xiaoyang Li, Wenhong Wang, Mingyu Fudan Univ State Key Lab ASIC & Syst Shanghai 200433 Peoples R China

ISBN: (纸本)9798350330991;9798350331004

This paper proposed a hardware-algorithm co-design of an event-driven Spiking Neural Network (SNN) accelerator with structured sparsity for Dynamic Vision Sensors (DVS) applications. The accelerator can accommodate up to 1024 neurons and 1 million synapses for a feed-forward fully connected SNN implementation. configurable structured sparsity is introduced by modular arithmetic both in the algorithm and hardware to improve the energy efficiency, reduce the memory requirement, and balance the workload between different processing elements. With an event-driven neuron update scheme, the accelerator can fully utilize the benefits of structured sparsity and can directly process DVS output data for classification tasks without encoding. A three-layer SNN is trained through backpropagation through time (BPTT) and is implemented on Xilinx ZCU104 FPGA, which achieves 96% accuracy on the N-MNIST dataset and 79% accuracy on the DVS-Gesture dataset both at 50% sparsity. The top performance of the accelerator on ZCU104 is 3.82 GSOP/S and 5.31 GSOP/W at 250 MHz.

关键词： Spiking Neural Networks Dynamic Vision Sensors hardware-algorithm co-design event-driven structured sparsity FPGA

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A 1Mb Mixed-Precision Quantized Encoder for Image Classification and Patch-Based compression

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY 2022年第8期32卷 5581-5594页

作者： Van Thien Nguyen Guicquero, William Sicard, Gilles Univ Grenoble Alpes CEA LETI F-38000 Grenoble France

Even if Application-Specific Integrated Circuits (ASIC) have proven to be a relevant choice for integrating inference at the edge, they are often limited in terms of applicability. In this paper, we demonstrate that an ASIC neural network accelerator dedicated to image processing can be applied to multiple tasks of different levels: image classification and compression, while requiring a very limited hardware. The key component is a reconfigurable, mixed-precision (3b/2b/1b) encoder that takes advantage of proper weight and activation quantizations combined with convolutional layer structural pruning to lower hardware-related constraints (memory and computing). We introduce an automatic adaptation of linear symmetric quantizer scaling factors to perform quantized levels equalization, aiming at stabilizing quinary and ternary weights training. In addition, a proposed layer-shared Bit-Shift Normalization significantly simplifies the implementation of the hardware-expensive Batch Normalization. For a specific configuration in which the encoder design only requires 1Mb, the classification accuracy reaches 87.5% on CIFAR-10. Besides, we also show that this quantized encoder can be used to compress image patch-by-patch while the reconstruction can performed remotely, by a dedicated full-frame decoder. This solution typically enables an end-to-end compression almost without any block artifacts, outperforming patch-based state-of-the-art techniques employing a patch-constant bitrate.

关键词： Quantization (signal) Image coding hardware Task analysis convolution Neural networks Training hardware-algorithm co-design quantization pruning autoencoder patch-based image compression

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GeMP-BNN: High-Performance Sampling-Free Bayesian Neural Network Accelerator with Gaussian Error Moment Propagation 16

GeMP-BNN: High-Performance Sampling-Free Bayesian Neural Net...

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16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)

作者： Hirayama, Yuki Suga, Kengo Takamaeda-Yamazaki, Shinya Univ Tokyo Tokyo Japan

ISBN: (纸本)9798350393613

Bayesian neural networks (BNNs), which can represent predictive uncertainty, have been an essential framework for reliable machine learning. Unfortunately, BNNs are difficult to use in applications requiring high-throughput processing, such as automated driving systems. This difficulty arises from the large amount of computation required, compared to that required for non-Bayesian neural networks. For example, Monte Carlo sampling-based BNNs require tens of forward propagations for prediction. Another approach, known as moment propagation, requires a lot of computations in the nonlinear layers, including exponential and square root functions, which are difficult to execute on hardware. Edge AI in IoT systems requires inference with limited computational resources, but the computation of such expensive functions results in increased circuit resources and increased computation. To realize high-throughput uncertainty estimation with limited computational resources, a hardware-friendly nonlinear layer and a dedicated hardware accelerator that can efficiently execute moment propagation are necessary. This study proposes a novel nonlinear layer, Gaussian error moment propagation (GeMP), which introduces nonlinearity and perturbations with less computational cost and no additional parameters and develops a dedicated FPGA-based accelerator utilizing the proposed nonlinear layer. Through evaluations with software and FPGA implementation, we showed that GeMP-BNN achieved up to 4.9 times higher throughput and 0.20 times lower energy consumption without compromising the uncertainty quality compared with BNN accelerators having previous nonlinear layers.

关键词： Bayesian neural network FPGA accelerator hardware-algorithm co-design Moment propagation Nonlinear layer

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Real-Time Acoustic Perception for Automotive Applications

Real-Time Acoustic Perception for Automotive Applications

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design, Automation and Test in Europe conference and Exhibition (DATE)

作者： Yin, Jun Damiano, Stefano Verhelst, Marian van Waterschoot, Toon Guntoro, Andre Katholieke Univ Leuven ESAT MICAS Leuven Belgium Katholieke Univ Leuven ESAT STADIUS Leuven Belgium Robert Bosch GmbH Gerlingen Germany

ISBN: (纸本)9798350396249

In recent years the automotive industry has been strongly promoting the development of smart cars, equipped with multi-modal sensors to gather information about the surroundings, in order to aid human drivers or make autonomous decisions. While the focus has mostly been on visual sensors, also acoustic events are crucial to detect situations that require a change in the driving behavior, such as a car honking, or the sirens of approaching emergency vehicles. In this paper, we summarize the results achieved so far in the Marie Sklodowska-Curie Actions (MSCA) Eruopean Industrial Doctorates (EID) project "Intelligent Ultra Low-Power Signal Processing for Automotive (I-SPOT)". On the algorithmic side, the I-SPOT Project aims to enable detecting, localizing and tracking environmental audio signals by jointly developing microphone array processing and deep learning techniques that specifically target automotive applications. Data generation software has been developed to cover the I-SPOT target scenarios and research challenges. This tool is currently being used to develop low-complexity deep learning techniques for emergency sound detection. On the hardware side, the goal impels workflows for hardware-algorithm co-design to ease the generation of architectures that are sufficiently flexible towards algorithmic evolutions without giving up on efficiency, as well as enable rapid feedback of hardware implications of algorithmic decision. This is pursued though a hierarchical workflow that breaks the hardware-algorithm design space into reasonable subsets, which has been tested for operator-level optimizations on state-of-the-art robust sound source localization for edge devices. Further, several open challenges towards an end-to-end system are clarified for the next stage of I-SPOT.

关键词： Acoustic Perception Sound Event Detection Sound Source Localization Embedded AI hardware-algorithm co-design Autonomous Driving Microphone Array Processing

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Energy-Efficient In-Memory Binary Neural Network Accelerator design Based on 8T2C SRAM Cell

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IEEE SOLID-STATE CIRCUITS LETTERS 2022年 5卷 70-73页

作者： Oh, Hyunmyung Kim, Hyungjun Ahn, Daehyun Park, Jihoon Kim, Yulhwa Lee, Inhwan Kim, Jae-Joon Pohang Univ Sci & Technol Dept Convergence IT Engn Pohang 37673 South Korea Pohang Univ Sci & Technol Future IT Innovat Lab Pohang 37673 South Korea Seoul Natl Univ Dept Elect & Comp Engn Seoul 08826 South Korea

We present an in-memory binary neural network (BNN) accelerator based on 8-transistor and 2-capacitor (8T2C) SRAM cell. The proposed SRAM computing-in-memory (CIM) cells rely on DRAM-like charge sharing operations to avoid undesirable static currents and potential read-disturb problems in conventional resistive SRAM-CIM designs. In addition, unlike the previous capacitive SRAM-based CIM designs, the proposed SRAM CIM does not consume energy when the input value is 0, thereby achieving the higher energy efficiency in benchmark testing. Measurement results of the 256 x 64 array prototype chip in the 28-nm CMOS technology showed 3182 TOPS/W at 0.7 V which is 4.7 x higher energy efficiency than that of a state-of-the-art design.

关键词： Binary neural network (BNN) charge sharing computing-in-memory (CIM) hardware-algorithm co-design SRAM

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algorithmic enablers for compact Neural Network topology hardware design: review and trends 52

Algorithmic enablers for compact Neural Network topology Har...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Guicquero, William Verdant, Arnaud CEA LETI F-38000 Grenoble France

ISBN: (纸本)9781728133201

This paper reports the main State-Of-The-Art algorithmic enablers for compact Neural Network topology design, while relying on basic numerical experiments. Embedding in-sensor intelligence to perform inference tasks generally requires a proper definition of a Neural Network architecture dedicated to specific purposes under hardware limitations. hardware design constraints known as power consumption, silicon surface, latency and maximum clock frequency cap available resources related to the topology, i.e., memory capacity and algorithmic complexity. We propose to categorize into 4 types the algorithmic enablers that force the hardware constraints as low as possible while keeping the accuracy as high as possible. First, Dimensionality Reduction (DR) is used to reduce memory needs thanks to predefined, hardware-coded patterns. Secondly, low-precision Quantization with Normalization (QN) can both simplify hardware components as well as limiting overall data storage. Thirdly, connectivity Pruning (CP) involves an improvement against over-fitting while limiting needless computations. Finally, during the inference at the feed-forward pass, a Dynamical Selective Execution (DSE) of topology parts can be performed to limit the activation of the entire topology, therefore reducing the overall power consumption.

关键词： Neural Network compressive Sensing Random Pruning Quantized Neural Network Dynamic Neural Network hardware-algorithm co-design

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