high quality videos became an essential requirement in recent applications. highefficiencyvideocoding (HEVC) standard provides an efficient solution for high quality videos at lower bit rates. On the other hand, HE...
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high quality videos became an essential requirement in recent applications. highefficiencyvideocoding (HEVC) standard provides an efficient solution for high quality videos at lower bit rates. On the other hand, HEVC comes with much higher computational cost. In particular, motion estimation (ME) in HEVC, consumes the largest amount of computations. Therefore, fast ME algorithms and hardware accelerators are proposed in order to speed-up integer ME in HEVC. This study presents a fast centre search algorithm (FCSA) and an adaptive search window algorithm (ASWA) for integer pixel ME in HEVC. In addition, centre adaptive search algorithm, a combination of the two proposed algorithms FCSA and ASWA, is proposed in order to achieve the best performance. Experimental results show notable speed-up in terms of encoding time and bit rate saving with tolerable peak signal-to-noise ratio (PSNR) quality degradation. The proposed fast search algorithms reduce the computational complexity of the HEVC encoder by 57%. This improvement is accompanied with a modest average PSNR loss of 0.014 dB and an increase by 0.6385% in terms of bit rate when compared with related works.
In highefficiencyvideocoding (HEVC) standard, higher video resolutions employ larger integer Discrete Cosine Transform (DCT)/inverse DCT (IDCT) block sizes. In this study, the authors propose two high-throughput un...
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In highefficiencyvideocoding (HEVC) standard, higher video resolutions employ larger integer Discrete Cosine Transform (DCT)/inverse DCT (IDCT) block sizes. In this study, the authors propose two high-throughput unified DCT/IDCT architectures. The proposed architectures can process variable DCT/IDCT block sizes according to the HEVC standard. The proposed architectures were prototyped on TSMC 65nm CMOS technology. The prototyping results show that the two unified architectures have throughput of 15.24 and 16.03Gsps, respectively, and they can encode video sequences with resolutions up to 8K at 120fps and decode the same resolution at 240fps using only one circuit for both DCT and IDCT.
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