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Optimised HEVC encoder intra-only configuration

IET COMPUTERS AND DIGITAL TECHNIQUES 2020年第6期14卷 256-262页

作者： Bahri, Nejmeddine Khemiri, Randa Univ Sfax Lab Elect & Informat Technol Natl Sch Engn Sfax Sfax Tunisia Univ Monastir Lab Elect & Microelect Fac Sci Monastir Monastir Tunisia

high-efficiency video coding (HEVC) is the latest video coding standard aimed to reduce the bitrate by half for the same video quality compared to H.264/AVC. This encoding performance makes HEVC more suitable for high-definition video applications. However, this performance is coupled with a high-computational complexity, which makes it hard to achieve real-time video encoding with a classic embedded processor. Multicore technology of programmable processors could be a very promising solution to overcome this computational complexity. Moreover, software optimisations by proposing fast algorithms for the most complex functions could also be an efficient solution to speed up the encoding process. In this context, this study presents a fast mode decision algorithm for the intra prediction module. This algorithm aims to reduce the number of intra prediction modes to be tested instead of performing a full intra mode search. Experimental results for all-Intra configuration show that the proposed fast intra mode decision allows saving up to 46.79% of the intra prediction time in average. Encoding performance in terms of video quality and bitrate is not significantly affected.

关键词： optimisation high definition video computational complexity data compression video coding high-efficiency video coding video coding standard video quality high-definition video applications high-computational complexity real-time video encoding embedded processor multicore technology software optimisations intra prediction modes HEVC encoder intra-only configuration optimization

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Accelerating motion estimation by genetic algorithm approach in x265

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JOURNAL OF ELECTRONIC IMAGING 2018年第6期27卷

作者： More, Vidya N. Bartakke, Prashant P. Sutaone, Mukul S. Coll Engn Pune Dept Elect & Telecommun Fac Engn Pune Maharashtra India

In the last two decades, in the domain of video coding and compression, researchers have suggested several techniques for computation and time reduction for motion estimation (ME). We present a motion estimation algorithm for x265 video codec, based on a deterministic initial population in the genetic algorithm (GA). GA is known for its adaptive convergence, which is motivated by the biological process of survival of the fittest. The suggested scheme is targeted for the reduction of search points (SP) in a block matching motion estimation algorithm for integer-pel in B and P frames that are set to have three reference frames. The initial population constituted in our approach is a function of pre-encoded coding units at different spatial-temporal locations of the video frames and predefined hexagonal (HEX) locations. We propose a "deterministically starting" GA (GADet), toward deployment in x256 structure. In the framework of x265 code, GADet is found to offer reduction in SP at selected classes of videos considered for experimentation. To demonstrate the effectiveness of the proposed work, results have been compared with the block-based fast-full-search algorithm and the HEX search algorithm from the reference software. Traditional GA with a randomly constituted initial population, labeled as GAStc, is also implemented and an empirical comparison is carried out with GADet. The proposed GADet framework provides reduction in motion estimation time while rendering acceptable peak signal-to-noise ratio loss and an increase in a bit rate. (C) 2018 SPIE and IS&T

关键词： motion estimation high-efficiency video coding evolutionary strategy genetic algorithm

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A 249-Mpixel/s HEVC video-Decoder Chip for 4K Ultra-HD Applications

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 2014年第1期49卷 61-72页

作者： Tikekar, Mehul Huang, Chao-Tsung Juvekar, Chiraag Sze, Vivienne Chandrakasan, Anantha P. MIT Cambridge MA 02139 USA Natl Tsing Hua Univ Hisnchu 30013 Taiwan

high efficiency video coding, the latest video standard, uses larger and variable-sized coding units and longer interpolation filters than H. 264/AVC to better exploit redundancy in video signals. These algorithmic techniques enable a 50% decrease in bitrate at the cost of computational complexity, external memory bandwidth, and, for ASIC implementations, on-chip SRAM of the video codec. This paper describes architectural optimizations for an HEVC video decoder chip. The chip uses a two-stage subpipelining scheme to reduce on-chip SRAM by 56 kbytes-a 32% reduction. A high-throughput read-only cache combined with DRAM-latency-aware memory mapping reduces DRAM bandwidth by 67%. The chip is built for HEVC Working Draft 4 Low Complexity configuration and occupies 1.77 mm(2) in 40-nm CMOS. It performs 4K Ultra HD 30-fps video decoding at 200 MHz while consuming 1.19 nJ/pixel of normalized system power.

关键词： DRAM bandwidth reduction entropy decoder high-efficiency video coding inverse discrete cosine transform (IDCT) motion compensation cache ultrahigh definition (ultra HD) video-decoder chip.

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Zero coefficient-aware fast butterfly-based inverse discrete cosine transform algorithm

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IET IMAGE PROCESSING 2016年第2期10卷 89-100页

作者： Park, Sang-hyo Choi, Kiho Jang, Euee S. Hanyang Univ Digital Media Lab Seoul 133791 South Korea

The latest video coding standards, including Moving Picture Experts Group-4 (MPEG-4) advanced video coding (AVC)/H.264 and high-efficiency video coding (HEVC), use a discrete cosine transform (DCT) process as the core for compression efficiency, sacrificing the computational complexity at decoder. There have been a number of attempts to reduce the complexity of inverse DCT (IDCT). Butterfly-based factorisation remains the most commonly used method for such a reduction. In this study, the authors propose a zero (Z) coefficient-aware fast butterfly-based IDCT algorithm for video decoding. They focus on a reduction in the computational complexity of the butterfly-based 8 x 8 IDCT by removing the unnecessary computations of one-dimensional (1D) IDCT kernels, and adaptively applying IDCT kernels based on the number of non-Z DCT coefficients to speed-up 1D data. Their experimental results show that the average operation numbers using the proposed IDCT is approximately half that for the 8 x 8 IDCT implemented in the MPEG-4 AVC/H.264 and HEVC reference software. The improved computational complexity of the proposed method is demonstrated by measuring the running time, which requires only one-half of the IDCT time using the reference software.

关键词： video coding inverse transforms discrete cosine transforms data compression computational complexity zero coefficient-aware fast butterfly-based IDCT algorithm inverse discrete cosine transform algorithm Moving Picture Experts Group-4 advanced video coding MPEG-4 H.264 high-efficiency video coding HEVC reference software inverse DCT algorithm compression efficiency computational complexity reduction butterfly-based factorisation 1D IDCT kernels non Z DCT coefficients

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ELECTRONICS LETTERS 2016年第12期52卷 1022-1023页

作者： Jiang, He Yang, Jie Shanghai Jiao Tong Univ Inst Image Proc & Pattern Recognit 800 Dongchuan Rd Shanghai Peoples R China

A low complexity but effective method in image and video detail enhancement - in-place similarity is proposed. In-place similarity is the statistic result of different kinds of nature image patches when similarity measurement is done in super resolution research, finding that patches in the upscale image have a good match around its original location in the corresponding lower ones. On the basis of the in-place similarity, a simple assumption is made that detail layer is the high-frequency component of twice search and patch match result. Then, images under the framework of super resolution techniques are enhanced. Unlike many current algorithms that need to adjust parameters for different images to acquire best outputs the approach mentioned here is adaptive. Moreover, many algorithms have outcome with intensity and contrast change, the algorithm proposed here can prevent images from over enhancement with obvious nature looking effect. Extensive experiments demonstrate that the algorithm mentioned here is simple with robust good performance both subjectively and objectively. It is particularly useful for practical applications and easily hardware implemented in FPGA, where input images require diverse detail textures.

关键词： image texture image coding motion estimation rate distortion theory adaptive search range neighbouring depth intensity weighted sum HEVC texture coding high-efficiency video coding H 264 AVC bitrate reduction perceptual quality motion estimation ME coding complexity depth map multiview plus depth video HEVC complexity reduction depth intensity variation neighbouring blocks motion vector weighted sum rate-distortion degradation

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Design of integer motion estimator of HEVC for asymmetric motion-partitioning mode and 4K-UHD

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ELECTRONICS LETTERS 2013年第18期49卷 1142-1143页

作者： Byun, J. Jung, Y. Kim, J. Yonsei Univ Sch Elect & Elect Engn Seoul 120749 South Korea

A design for an integer motion estimator of high-efficiency video coding (HEVC) is presented. HEVC supports the 64 x 64 coding tree unit, the recursive quad-tree coding unit structure and the asymmetric motion-partitioning mode in a high compression ratio. These features require a structure of integer motion estimation that is more complex than that of H. 264/AVC. The new structures of a memory read controller and a sum of absolute difference (SAD) summation block are proposed. The new memory read controller reduces the internal memory read time, and the new SAD summation block structure supports the recursive quad-tree coding unit structure and the asymmetric motion-partitioning mode. The proposed design is implemented in Verilog HDL and synthesised using the 65 nm CMOS technology. The gate count is 3.56 M, and the internal static random access memory is about 20 kbyte. The operation frequency is 250 MHz when a 4 K-Ultra high definition (UHD) (3840 x 2160P at 30 Hz) sized video is encoded.

关键词： trees (mathematics) frequency 250 MHz Verilog HDL CMOS digital integrated circuits asymmetric motion-partitioning mode frequency 30 Hz internal SRAM CMOS technology internal memory read time reduction integer motion estimator design video codecs data compression sum of absolute difference summation block SRAM chips SAD summation block structure Combinatorial mathematics recursive quad-tree coding unit structure CMOS integrated circuits size 65 nm Semiconductor storage high compression ratio Logic design methods high-efficiency video coding hardware description languages recursive estimation Computer vision and image processing techniques Other topics in statistics motion estimation gate count HEVC Image and video coding 4 K-UHD H.264-AVC Memory circuits video signal processing memory read controller video coding

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Thumbnail extraction for HEVC using prediction modes

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ELECTRONICS LETTERS 2015年第6期51卷 480-481页

作者： Lee, Wonjin Jeon, Gwanggil Jeong, Jechang Hanyang Univ Dept Elect & Comp Engn Seoul South Korea Incheon Natl Univ Dept Embedded Syst Engn Inchon South Korea

The existing thumbnail extraction method generates a thumbnail by reducing the reconstructed frame after a full decoding process. This method is complex and requires considerable time, particularly for higher resolution video. To alleviate these issues, a fast thumbnail extraction method which utilises an intra-prediction mode for high-efficiency video coding (HEVC) is presented. The proposed method reconstructs only the 4x4 boundary pixels needed for a thumbnail image based on the intra-prediction mode. Experimental results indicate that the proposed method significantly reduces the computational complexity and extraction time for a thumbnail image. The visual quality of thumbnail images obtained with this method does not differ significantly from that of images extracted after a full decoding process.

关键词： video coding computational complexity prediction unit pruning algorithm high-efficiency video coding inter-prediction HEVC computational complexity video coding standards inter prediction algorithm computational load inter-mode decision time

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Model selection for mixture model via integrated nested Laplace approximation

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ELECTRONICS LETTERS 2015年第6期51卷 484-485页

作者： Yoon, Ji Won Korea Univ Seoul South Korea

To cluster or partition data/signal, expectation-and-maximisation or variational approximation with a mixture model (MM), which is a parametric probability density function represented as a weighted sum of (K) over cap densities, is often used. However, model selection to find the underlying (K) over cap is one of the key concerns in MM clustering, since the desired clusters can be obtained only when (K) over cap is known. A new model selection algorithm to explore (K) over cap in a Bayesian framework is proposed. The proposed algorithm builds the density of the model order which information criterion such as AIC and BIC or other heuristic algorithms basically fail to reconstruct. In addition, this algorithm reconstructs the density quickly as compared with the time-consuming Monte Carlo simulation using integrated nested Laplace approximation.

关键词： video coding image resolution image reconstruction extraction time computational complexity 4x4 boundary pixels high-efficiency video coding intra-prediction mode fast thumbnail extraction method HEVC prediction modes

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A Practical System towards the Secure, Robust and Pervasive Mobile Workstyle 85

A Practical System towards the Secure, Robust and Pervasive ...

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IEEE 85th Vehicular Technology Conference (VTC Spring)

作者： Ma, Zhan Yue, Tao Cao, Xun Xu, Yiling Li, Xin Wang, Yongjin Nanjing Univ Nanjing Jiangsu Peoples R China Shanghai Jiao Tong Univ Shanghai Peoples R China Yun Ge Zhi Li Inc Richardson TX USA Nanjing Univ Posts & Telecommun Nanjing Jiangsu Peoples R China

ISBN: (纸本)9781509059324

We develop an innovative PC2PC (personal computer to pervasive computing) system to enable the secure, robust and pervasive mobile workstyle. PC2PC server compresses the desktop screens of any virtualized system, and delivers the stream through any popular networks to PC2PC client remotely for stream decoding, rendering and end-user interaction (such as keyboard/ mouse commands). We have implemented the overall system from the scratch, where the emerging screen content coding (SCC) extension of the high-efficiency video coding (HEVC) is implemented to compress and stream the desktop screens in real-time, and three core asset channels (i.e., system, display, inputs, etc) are defined to enable systematic end-to-end communication. Compared with the commercial Red Hat SPICE virtual desktop infrastructure (VDI) scheme, our PC2PC could save the network bandwidth by a factor of 2, 7 and 4 respectively for typical video streaming, web browsing and stationary office applications at same visual quality. Meanwhile, we have also measured the delays in the system and presented the preliminary study on the user experience impact. A simple network estimation is applied to optimize the quality-bandwidth adaptation for both single user and multiuser scenarios to combat the network dynamics.

关键词： Pervasive computing virtual desktop infrastructure high-efficiency video coding screen content coding

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Accelerating HEVC Transcoder by Exploiting Decoded Quadtree

Accelerating HEVC Transcoder by Exploiting Decoded Quadtree

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18th IEEE International Symposium on Consumer Electronics (ISCE)

作者： Sung, Minyong Kim, Minwoo Kim, Minsik Ro, Won Woo Yonsei Univ Sch Elect & Elect Engn Seoul 120749 South Korea

ISBN: (纸本)9781479945917

This paper proposes an accelerated high-efficiency video coding (HEVC) transcoder which can promptly provide downscaled video contents to various devices. The quadtree information is first extracted from the decoding process and is transformed for the target resolution. By utilizing the decoded depth information, the encoder can be accelerated by only searching the optimal depths in the quadtree, without losing the video quality. The encoder also adaptively changes the depth search ranges according to the picture order count (POC) for further optimization. Our proposed method shows a maximum encoding speedup of 2.18, with only 0.3% BD-rate increase in the best case.

关键词： transcoding high-efficiency video coding depth skip decoding information reuse

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