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检索条件"主题词=hyper loop parallelism"

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Efficient Exploitation of hyper loop parallelism in Vectorization 27

Efficient Exploitation of Hyper Loop Parallelism in Vectoriz...

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27th International Workshop on Languages and Compilers for Parallel Computing (LCPC)

作者： Xu, Shixiong Gregg, David Univ Dublin Trinity Coll Lero Dublin Ireland Univ Dublin Trinity Coll Dept Comp Sci Software Tools Grp Dublin Ireland

ISBN: (纸本)9783319174730;9783319174723

Modern processors can provide large amounts of processing power with vector SIMD units if the compiler or programmer can vectorize their code. With the advance of SIMD support in commodity processors, more and more advanced features are introduced, such as flexible SIMD lane-wise operations (e.g. blend instructions). However, existing vectorizing techniques fail to apply global SIMD lane-wise optimization due to the unawareness of the computation structure of the vectorizable loop. In this paper, we put forward an approach to automatic vectorization based on hyper loop parallelism, which is exposed by hyper loops. hyper loops recover the loop structures of the vectorizable loop and help vectorization to apply global SIMD lane-wise optimization. We implemented our vectorizing technique in the Cetus source-to-source compiler to generate C code with SIMD intrinsics. The preliminary experimental results show that our vectorizing technique can achieve significant speedups up over the non-vectorized code in our test cases.

关键词： hyper loop parallelism Automatic vectorization Global SIMD lane-wise optimization SIMD

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Exploiting hyper-loop parallelism in Vectorization to Improve Memory Performance on CUDA GPGPU 14

Exploiting Hyper-Loop Parallelism in Vectorization to Improv...

引用

13th IEEE International Symposium on Parallel and Distributed Processing with Applications

作者： Xu, Shixiong Gregg, David Univ Dublin Trinity Coll Dept Comp Sci Software Tools Grp Dublin Ireland Lero Limerick Ireland

ISBN: (纸本)9781467379526

Memory performance is of great importance to achieve high performance on the Nvidia CUDA GPU. Previous work has proposed specific optimizations such as thread coarsening, caching data in shared memory, and global data layout transformation. We argue that vectorization based on hyper loop parallelism can be used as a unified technique to optimize the memory performance. In this paper, we put forward a compiler framework based on the Cetus source-to-source compiler to improve the memory performance on the CUDA GPU by efficiently exploiting hyper loop parallelism in vectorization. We introduce abstractions of SIMD vectors and SIMD operations that match the execution model and memory model of the CUDA GPU, along with three different execution mapping strategies for efficiently offloading vectorized code to CUDA GPUs. In addition, as we employ the vectorization in C-to-CUDA with automatic parallelization, our technique further refines the mapping granularity between coarse-grain loop parallelism and GPU threads. We evaluated our proposed technique on two platforms, an embedded GPU system - Jetson TK1 - and a desktop GPU - GeForce GTX 645. The experimental results demonstrate that our vectorization technique based on hyper loop parallelism can yield performance speedups up to 2.5x compared to the direct coarse-grain loop parallelism mapping.

关键词： vectorization hyper loop parallelism thread coarsening memory performance CUDA GPU

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Exploiting hyper-loop parallelism in Vectorization to Improve Memory Performance on CUDA GPGPU

Exploiting Hyper-Loop Parallelism in Vectorization to Improv...

引用

IEEE International Symposium on Parallel and Distributed Processing with Applications

作者： Shixiong Xu David Gregg Software Tools Group Department of Computer Science Trinity College The University of Dublin Ireland Lero The Irish Software Engineering Research Centre

ISBN: (纸本)9781467379533

Memory performance is of great importance to achieve high performance on the Nvidia CUDA GPU. Previous work has proposed specific optimizations such as thread coarsening, caching data in shared memory, and global data layout transformation. We argue that vectorization based on hyper loop parallelism can be used as a unified technique to optimize the memory performance. In this paper, we put forward a compiler framework based on the Cetus source-tosource compiler to improve the memory performance on the CUDA GPU by efficiently exploiting hyper loop parallelism in vectorization. We introduce abstractions of SIMD vectors and SIMD operations that match the execution model and memory model of the CUDA GPU, along with three different execution mapping strategies for efficiently offloading vectorized code to CUDA GPUs. In addition, as we employ the vectorization in C-to-CUDA with automatic parallelization, our technique further refines the mapping granularity between coarse-grain loop parallelism and GPU threads. We evaluated our proposed technique on two platforms, an embedded GPU system —Jetson TK1 — and a desktop GPU - GeForce GTX 645. The experimental results demonstrate that our vectorization technique based on hyper loop parallelism can yield performance speedups up to 2.5 x compared to the direct coarse-grain loop parallelism mapping.

关键词： vectorization hyper loop parallelism thread coarsening memory performance CUDA GPU

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