At present the best methods for rotation of discrete sampled images use a combination of (fast) Fourier interpolation followed by cubic interpolation onto a rotated grid. A method is presented which uses only Fourier ...
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At present the best methods for rotation of discrete sampled images use a combination of (fast) Fourier interpolation followed by cubic interpolation onto a rotated grid. A method is presented which uses only Fourier interpolation. The new method has a similar computational complexity to the old, and is exactly reversible. The method uses the well-known decomposition of rotation into three pure shears. Each shear is performed using a 2D extension of the 1D Fourier shift theorem. This allows the fast Fourier transform (FFT) to be used, With appropriate data padding (such as zero padding) in both the real and Fourier domains, the procedure gives near perfect results and minimal loss of information in multiple rotation tests.
In this paper, we propose the architecture of a highly parallel DSP (HiPAR-DSP) as a flexible and programmable processor for image and video processing. The design of this processor is based on an analysis of characte...
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In this paper, we propose the architecture of a highly parallel DSP (HiPAR-DSP) as a flexible and programmable processor for image and video processing. The design of this processor is based on an analysis of characteristic properties of image processing algorithms in terms of available parallelization resources, demands on program control, and required data access mechanisms. This led to a very long instruction word (VLIW)-controlled ASIMD RISC-architecture with four or sixteen data paths, employing data-level parallelism, parallel instructions, micro-instruction pipelining, and data transfer concurrently to data processing. Common data access patterns for image processing algorithms are supported by use of a shared on-chip memory with parallel matrix type access patterns and a separate data-cache per data path, By properly balancing processing and controlling capabilities as internal and external memory bandwidth, this approach is optimized to make best use of currently available silicon resources. A high clock frequency is achieved by implementation of classic RISC features. The architecture fully supports high level language programming. With the 16 data path version at 100 MHz clock, a sustained performance of more than 2 billion arithmetic operations per second (GOPS) is achieved for a wide range of algorithms. Given examples show the parallel implementation of image processing algorithms like histogramming, Hough transform, or search in a sorted list with efficient use of the processor resources. A prototype of the architecture with four parallel data paths will be available in the second quarter of 1996, using a 0.6 mu m CMOS technology.
The problem of memory contention in digital scan converters (DSC) is discussed. The role of the microprocessor in DSC design is examined, and the importance of uninterrupted display in the development and use of image...
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The problem of memory contention in digital scan converters (DSC) is discussed. The role of the microprocessor in DSC design is examined, and the importance of uninterrupted display in the development and use of image-processingalgorithms is stressed. The drawbacks inherent in interrupt and in direct memory access are pointed out and an elegant scheme using the CPU ‘READY’ feature is suggested as an alternative, cycles during which memory contention could occur are predictable, and during these cycles the CPU is prevented from addressing the store. A specific implementation is described using the TMS9900 microprocessor in a DSC displaying sector-scanned sonar images. Timing problems are discussed in detail.
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