The Group for Quality Assurance and Industrial image Processing has built a new experimental setup to characterize cameras and imagesensors according to EMVA1288 standard. Next to the investigation of SLN (Sensitivit...
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ISBN:
(数字)9781510618244
ISBN:
(纸本)9781510618244
The Group for Quality Assurance and Industrial image Processing has built a new experimental setup to characterize cameras and imagesensors according to EMVA1288 standard. Next to the investigation of SLN (Sensitivity-Linearity-Noise) and spatial non-uniformities, the new test bench also provides an examination of the temperature dependence of sensors. The temperature dependent dark current produces an undesirable signal which affects the image quality negative and thus has to be known. It is caused by thermally induced electrons and increases linearly with exposure time as well as exponentially with temperature. To measure the dark current, it is necessary to vary and determine the temperature of the sensor. This was made possible by a climate chamber with a Peltier element, which enables a heating and cooling of the camera. An infrared sensor allows a contact-free detection of the actual camera temperature. Furthermore, the light source was improved for the new test bench. With the installed custom light source and integration sphere a homogeneous irradiation up to 97% is ensured. This way better results in tests were achieved. The light source with variable filter housing enables the use of monochromatically light in a wavelength range of 350 - 1700nm. A live monitoring of the irradiation during the image capturing is possible. A MATL AB script assists in the configuration of the camera, the measurement and the data storage. The user is guided step by step through the program. At the end of the measurements an automated evaluation follows, which illustrates graphs and parameters in a streamlined and print-ready format.
FPGAs are a key enabling technology for rapid and efficient system prototyping and initial commissioning of newly developed integrated circuits. One major aspect is the setup and control of interface components betwee...
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ISBN:
(纸本)9781479959440
FPGAs are a key enabling technology for rapid and efficient system prototyping and initial commissioning of newly developed integrated circuits. One major aspect is the setup and control of interface components between devices under test (DUT) and the FPGA infrastructure. So, as to maintain high flexibility in conjunction with the ability to deal with changes of requirements and use cases, as well as unforeseen or faulty behavior of the DUT, we propose a novel reconfigurable hardware/software infrastructure. IP blocks, such as register files or interface components to external hardware are attached as leafs to a tree-like communication system optimized for alterations. It is designed as an Embedded Linux compatible CPU subsystem to be accessed from user space via a uniform and portable kernel driver. Thus, it implements transparent access to custom functionality from user applications without specific knowledge concerning the hardware/software coupling.
Implementation and test results of an array for image applications with full-frame analog memory is presented. The array was implemented using 1.0 mu m double metal, single poly n-well standard CMOS technology. The se...
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ISBN:
(纸本)0819431206
Implementation and test results of an array for image applications with full-frame analog memory is presented. The array was implemented using 1.0 mu m double metal, single poly n-well standard CMOS technology. The sensor consists of a 24x24 pixels square array and circuitry for random access readout. A pixel is composed by a phototransistor and control circuitry to regulate the exposure time to light of phototransistors. Each pixel also includes an analog memory implemented using MOSFET capacitors. The output buffer drives the capacitance of the output line. The system requires a total core area of 5 mm(3). Tests were performed for each individual pixels and for the complete array. The voltage output as a function of integration time under different illumination levels shows a linear behaviour. Varying the exposure time is possible to change the detector sensitivity. The fixed pattern noise was 0.58 % of saturation level (3.5V). Memory capabilities were also tested, allowing non-destructive reading and a storage time over few seconds without a significant degradation.
Fixed pattern noise (FPN) for a CCD sensor is modeled as a sample of a spatial white noise process. This model is, however, not adequate for characterizing FPN in CMOS sensors, since the readout circuitry of CMOS sens...
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ISBN:
(纸本)0819427411
Fixed pattern noise (FPN) for a CCD sensor is modeled as a sample of a spatial white noise process. This model is, however, not adequate for characterizing FPN in CMOS sensors, since the readout circuitry of CMOS sensors and CCDs are very different. The paper presents a model for CMOS FPN as the sum of two components: a column and a pixel component. Each component is modeled by a first order isotropic autoregressive random process, and each component is assumed to be uncorrelated with the other. The parameters of the processes characterize each component of the FPN and the correlations between neighboring pixels and neighboring columns for a batch of sensors. We show how to estimate the model parameters from a set of measurements, and report estimates for 64x64 passive pixel sensor (PPS) and active pixel sensor (APS) test structures implemented in a 0.35 micron CMOS process. High spatial correlations between pixel components were measured for the PPS structures, and between the column components in both PPS and APS. The APS pixel components were uncorrelated.
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