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A Retargetable Framework for instruction-Set Architecture Simulation

ACM Transactions on Embedded Computing Systems 2006年第2期5卷 431-452页

作者： Reshadi, Mehrdad Dutt, Nikil Mishra, Prabhat University of California Center for Embedded Computer Systems Irvine CA 92697 United States University of Florida Department Computer and Information Science and Engineering FL 32611 United States

instruction-set architecture (ISA) simulators are an integral part of today's processor and software design process. While increasing complexity of the architectures demands high-performance simulation, the increasing variety of available architectures makes retargetability a critical feature of an instruction-set simulator. Retargetability requires generic models while high-performance demands target specific customizations. To address these contradictory requirements, we have developed a generic instruction model and a generic decode algorithm that facilitates easy and efficient retargetability of the ISA-simulator for a wide range of processor architectures, such as RISC, CISC, VLIW, and variable length instruction-set processors. The instruction model is used to generate compact and easy to debug instruction descriptions that are very similar to that of architecture manual. These descriptions are used to generate high-performance simulators. Our retargetable framework combines the flexibility of interpretive simulation with the speed of compiled simulation. The generation of the simulator is completely separate from the simulation engine. Hence, we can incorporate any fast simulation technique in our retargetable framework without introducing any performance penalty. To demonstrate this, we have incorporated fast IS-CS simulation engine in our retargetable framework which has generated 70% performance improvement over the best known simulators in this category. We illustrate the retargetability of our approach using two popular, yet different, realistic architectures: the SPARC and the ARM. © instruction-set architecture (ISA) simulators are an integral part of today's processor and software design process. While increasing complexity of the architectures demands high-performance simulation, the increasing variety of available architectures makes retargetability a critical feature of an instruction-set simulator. Retargetability requires generic models while hig

关键词： architecture description language decode algorithm Design generic instruction model instruction binary encoding Language Performance Retargetable instruction-set simulation

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An efficient retargetable framework for instruction-set simulation 03

An efficient retargetable framework for instruction-set simu...

引用

1st IEEE/ACM/IFIP International Conference on Hardward/Software Codesign and System Synthesis

作者： Reshadi, M Bansal, N Mishra, P Dutt, N Univ Calif Irvine Ctr Embedded Comp Syst Irvine CA 92717 USA

ISBN: (纸本)1581137427

关键词： retargetable instruction-set simulation generic instruction model instruction binary encoding decode algorithm architecture description language

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