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2nd International Conference on Genetic and Evolutionary Computing

作者： Xiang YunZhu Ding YueHua WuHan Polytech Univ Dept Comp Sci & Informat Engineer Wuhan 430023 Hubei Province Peoples R China

ISBN: (纸本)9780769533346

This paper introduces architecture and feature of 32-bit micro-processor, and describes internal data path in processor. Through analysis of function and theory of RISC CPU instruction decoder module, we design instruction decoder(ID) module of 32-bit CPU by pipeline theory. The instruction decoder includes register file, write back data to register file, sign bit extend, relativity check, and it is simulated on QuartusII successfully. Static time sequence shows the instruction decode module completing required unction.

关键词： instruction decoder channels (data transmission) central processing units RNA-Induced Silencing Complex Reduced instruction set computers PROCESSOR register file ARCHITECTURE Building construction

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An Efficient Fault-Tolerant instruction decoder for RISC-V Based Dual-Core Soft-Processors

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2023年第12期70卷 4816-4825页

作者： Shukla, Satyam Utkarsh, Md Azam, Md Ray, Kailash Chandra Indian Inst Technol Patna Dept Elect Engn Patna 801106 Bihar India

In the modern era, FPGA-based soft-core processors have gained much attention in space applications due to their flexibility and ease of integration. In such applications, radiation can produce a Single Event Upset (SEU) in CMOS devices that may lead to severe errors in microprocessors. The instruction decoder is one of the most critical components of a microprocessor. Any error in the instruction decoder due to SEU may destroy the flow of the program, and it may lead to complete system failure. Hence, a novel parity-based fault-tolerant instruction decoder architecture is proposed for dual-core processors implemented on FPGAs. In case of occurrence of SEU, the instruction decoders of two cores are swapped for fault-masking against single-bit error. Looking at the increased adaptability of RISC-V ISA, the proposed fault-tolerant instruction decoder is integrated with an in-house designed RV32IM processor using Verilog HDL. Further, the proposed fault-tolerant processor architecture is prototyped on commercially available NEXYS4 DDR FPGA board by employing the soft error mitigation (SEM) IP core of Xilinx Inc. to inject SEU in real time to study the fault tolerance capability. The proposed design is compared with the state-of-the-art SEU mitigation approaches. The main advantage of the proposed architecture is that the LUT (Look up table) overhead is 167.06% less, and power overhead is 46.87% less compared to the conventional triple modular redundancy (TMR) approach to mitigate SEU. The proposed design is able to provide 71.2% fault tolerance compared to the unprotected design.

关键词： Decoding Fault tolerant systems Program processors Registers Field programmable gate arrays Circuit faults Redundancy instruction decoder fault-tolerant design RISC-V processor architectural design FPGA prototype

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Hardware Software Co-design of Pipelined instruction decoder in System Emulation

Hardware Software Co-design of Pipelined Instruction Decoder...

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2013 IEEE 4th International Conference on Software Engineering and Service Science

作者： Sichun Zhang Liehui Jiang Xiaojuan Zhang Xiaolong Hu China National Digital Switching System Engineering and Technological Research Center

ISBN: (纸本)9781467349994

System emulation based on dynamic binary translation can solve the problems of compatibility between heterogeneous *** on this field is mostly based on software,the efficiency is very low and restricting the performance of X86 system *** paper presents hardware software codesign of pipelined instruction decoder to avoid the inefficiency of system emulator based on *** decoder is controlled by the software unit and supported by the hardware unit via *** to system emulator based on software,the average speedup of pipelined instruction decoder achieves 5.2 and there is a significant performance improvement on system emulation.

关键词： pipelined stages co-design instruction decoder length of instruction system emulation

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TCC: GPGPU Architecture for instruction decoder and Control Flow Error Detection 27

TCC: GPGPU Architecture for Instruction Decoder and Control ...

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27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS)

作者： Raghunandana, K. K. Prasad, Yogesh K. R. Reorda, M. Sonza Singh, Virendra UR Rao Satellite Ctr Bangalore Karnataka India Politecn Torino Turin Italy Indian Inst Technol Mumbai Maharashtra India

ISBN: (纸本)9798350359343

The devices fabricated with the latest sub-nanometer technology node have a higher probability of parametric and wear-out failures, operational faults, and manufacturing defects, and these devices are more susceptible to intrinsic and extrinsic noise, resulting in soft errors. The parts with manufacturing defects are generally screened out during end-of-manufacturing tests. Thus, the soft errors during normal operations are of great concern. The soft errors in GPGPUs result into silent data corruption and control flow divergence errors. In order to deal with this, dual and triple modular redundancy architectures are used for soft error detection and correction, which result in large areas and power overheads. To overcome this, we propose a low overhead fault-tolerant microarchitecture called Trace Consistency Check (TCC) to detect the decoder and control flow divergence errors. The TCC is transparent to the application software. For error detection, we exploit the execution model of GPGPUs, where the warps of kernel executing in the streaming multiprocessor have temporal execution repetition. Hence, the instruction execution trace and control divergence paths across the warps are consistent. Inconsistency across warps for the same code region is attributed to decoder or control divergence errors. For error detection, new microarchitecture structures called Execution Trace buffer and Control Divergence Trace buffer were introduced to store and check the trace consistency across warps. The performance of TCC is evaluated through the ISPASS 2009 and RODINIA benchmarks. TCC's error detection capability and power overheads are evaluated. The simulation results show that TCC detects greater than 99% decoder and control flow errors with low power and no performance overheads.

关键词： GPGPU Fault-tolerant Redundant Error Detection instruction decoder control divergence

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Decomposition of instruction decoders for low-power designs

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ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS 2006年第4期11卷 880-889页

作者： Kuo, Wu-An Hwang, Tingting Wu, Allen C. -H. Natl Tsing Hua Univ Dept Comp Sci Hsinchu 300 Taiwan

During the execution of processor instruction, decoding the instructions is a major task in identifying instructions and generating control signals for data paths. In this article, we propose two instruction decoder decomposition techniques for low-power designs. First, by tracing program execution sequences, we propose an algorithm that explores the relations between frequently executed instructions. Second, we propose a two-stage low-power decomposition structure for decoding instructions. Experimental results demonstrate that our proposed techniques achieve an average of 34.18% in power reduction and 12.93% in critical-path delay reduction for the instruction decoder.

关键词： design low power instruction decoder

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A Prototype Design for Microprocessor based on Verilog HDL

A Prototype Design for Microprocessor based on Verilog HDL

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International Conference for Convergence of Technology (I2CT)

作者： Hinsu, Nikunj Suryavanshi, Digvijaysinh UV Patel Coll Engn & Technol VLSI Kherva Mehsana India

ISBN: (纸本)9781479937592

Nowadays for developing any embedded system the microprocessor is used extensively, but they comes to any developer as an black-box in which signals are provided from one side and corresponding output is extracted out from other side. So if developer knows what is hardware present inside the processor which he/she is currently using, then it would be helpful for making his/her design simple & optimized. In this paper, we have represented the design and simulation result of basic three elementary modules of microprocessor i.e. ALU, RAM and instruction decoder and finally combined all three modules using Structural modelling. This four bit processor has been designed as a prototype for designing advanced processors.

关键词： Processor ALU (Arithmetic and Logical Unit) RAM (Random Access Memory) instruction decoder Verilog HDL (Hardware Description Selection) Xilinx ISE

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SHRINK: Reducing the ISA Complexity Via instruction Recycling 15

SHRINK: Reducing the ISA Complexity Via Instruction Recyclin...

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ACM/IEEE 42nd Annual International Symposium on Computer Architecture (ISCA)

作者： Lopes, Bruno Cardoso Auler, Rafael Ramos, Luiz Bonin, Edson Azevedo, Rodolfo Univ Estadual Campinas UNICAMP Campinas SP Brazil

ISBN: (纸本)9781450334020

Microprocessor manufacturers typically keep old instruction sets in modern processors to ensure backward compatibility with legacy software. The introduction of newer extensions to the ISA increases the design complexity of microprocessor front-ends, exacerbates the consumption of precious on-chip resources (e.g., silicon area and energy), and demands more efforts for hardware verification and debugging. We analyzed several x86 applications and operating systems deployed between 1995 and 2012 and observed that many instructions stop being used over time, and more than 500 instructions were never used in these applications. We also investigate the impact of including these unused instructions in the design of the x86 decoders and propose SHRINK, a mechanism to remove old instructions without breaking backward compatibility with legacy code. SHRINK allows us to remove 40% of the instructions from the x86 ISA and improve the critical path, area, and power consumption of the instruction decoder;respectively, by 23%, 48%, and 49%, on average.

关键词： backward compatibility instruction instruction decoder legacy software Operating systems Debugging macroprocessor Power consumption

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Intel :: Iapx 432 :: 171873-001 Iapx 43201 Iapx 43202 Vlsi General Data Processor Feb81

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2016年

Intel :: Iapx 432 :: 171873-001 Iapx 43201 Iapx 43202 Vlsi General Data Processor Feb81 by published by

关键词： acd data error detection feb81 general hardware error iapx instruction decoder integer iny iapx ipc ordinal packet bus processor processor packet prq real short short integer short ordinal short real temporary real

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Hp :: 2116 :: 5950-8704 2116B Classvol2

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2016年

Hp :: 2116 :: 5950-8704 2116B Classvol2 by published by

关键词： 2116b classvol2 control card front panel gate instruction instruction decoder interface card interrupt interrupt system logic memory memory write output phase select code signal switch register timing timing generator true output

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GDSL: A Generic decoder Specification Language for Interpreting Machine Language

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ELECTRONIC NOTES IN THEORETICAL COMPUTER SCIENCE 2012年 289卷 53-64页

作者： Sepp, Alexander Kranz, Julian Simon, Axel Tech Univ Munich D-85748 Garching Germany

The analysis of executable code requires the reconstruction of instructions from a sequence of bytes (or words) and a specification of their semantics. Most front-ends addressing this problem only support a single architecture, are bound to a specific programming language, or are hard to maintain. In this work, we present a domain specific language (DSL) called GDSL (Generic decoder Specification Language) for specifying maintainable instruction decoders and the translation of instructions to a semantics. We motivate its design by illustrating its use for the Intel x86 platform. A compiler is presented that generates C code that rivals hand-crafted decoder implementations.

关键词： executable analysis binary analysis instruction decoder program semantics

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