The hardware/software co-reconfiguration technique is introduced to design a reconfigurable multimedia architecture that does not employ field-programmable devices. This co-reconfiguration technique does not require m...
详细信息
ISBN:
(纸本)9780780397835
The hardware/software co-reconfiguration technique is introduced to design a reconfigurable multimedia architecture that does not employ field-programmable devices. This co-reconfiguration technique does not require modifying existing compilers to retarget their new multimedia processors. This technique allows software developers to rapidly retarget their multimedia processors. In order to present the reconfiguration procedures and performance evaluations of the technique, a smart instruction decoder for Texas Instruments OMAP2420 was implemented and optimized
In very deep sub-micron designs, cross coupling capacitances become the dominant factor of the total bus loading and have a significant impact on the power consumption. In this paper, we propose two reconfigurable bus...
详细信息
ISBN:
(纸本)9780769520858
In very deep sub-micron designs, cross coupling capacitances become the dominant factor of the total bus loading and have a significant impact on the power consumption. In this paper, we propose two reconfigurable bus encoding schemes, which are based on the correlation among the bit lines, to reduce the power consumption at the cross coupling capacitances of the instruction buses. The instruction is encoded by flipping and reordering the bit lines during compilation time to reduce the total switching capacitances. A crossbar is used to map back the data to the original instruction code before sending to the instruction decoder. The reordering can be re-configured during run-time by using different configurations in the crossbar. We propose two types of re-configuration, static and dynamic. Static coding uses afix flipping and re-configuring pattern after the corresponding program is compiled. Dynamic coding allows different re-configuring patterns during program execution. Experimental results show that by using the proposed schemes, significant energy reduction, 17-23%, can be achieved. Comparisons with existing bit lines reordering encoding scheme have also been made and on average more than 15% reduction can be obtained using our method.
暂无评论