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International Conference on Intelligent Computing and Information Science

作者： Hu, Guang Chai, Zhilei Zhao, Wenke Shanghai Int Studies Univ Dept Comp Sci Shanghai 200086 Peoples R China Fudan Univ Sch Comp Sci Shanghai 200433 Peoples R China Jiangnan Univ Sch Internet Things Wuxi 214122 Peoples R China Intel Corp Intel Asia Pacific Res & Dev Ltd Shanghai 200241 Peoples R China

ISBN: (纸本)9783642181337

Now, as a popular language for the development of sever and desktop applications, Java is also playing a more and more important role in embedded development owning to its features like platform independence, high development efficiency, etc. Accordingly, JPOR-32, a 32-bit Java processor optimized for real-time specification for Java, is designed. In this paper, taking JPOR-32 as an example, the instruction execution stage design for embedded real-time Java processor is presented. The run time operand stack and method stack is implemented, which lays the foundations of execution of instruction set based on stack. For instruction execution stage, this paper presents on emphasis the control signal operation mechanism and the instruction execution stage data path.

关键词： Java processor real-time Java instruction execution real-time system

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A LOAD-instruction UNIT FOR PIPELINED PROCESSORS

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IBM JOURNAL OF RESEARCH AND DEVELOPMENT 1993年第4期37卷 547-564页

作者： EICKEMEYER, RJ VASSILIADIS, S IBM CORP ENTERPRISE SYSTMIDHUDSON VALLEY LABPOUGHKEEPSIENY 12602

A special-purpose load unit is proposed as part of a processor design. The unit prefetches date from the cache by predicting the address of the data fetch in advance. This prefetch allows the cache access to take place early, in an otherwise unused cache cycle, eliminating one cycle from the load instruction. The prediction also allows the cache to prefetch data if they are not already in the cache. The cache-miss handling can be overlapped with other instruction execution. It is shown, using trace-driven simulations, that the proposed mechanism, when incorporated in a design, may contribute to a significant increase in processor performance. The paper also compares different prediction methods and describes a hardware implementation for the load unit.

关键词： .data cache cache misses cache access prefetches processor performance load instruction Enterprise Systems instruction execution load unit

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A Microarchitecture for a Superconducting Quantum Processor

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IEEE MICRO 2018年第3期38卷 40-47页

作者： Fu, X. Rol, M. A. Bultink, C. C. van Someren, J. Khammassi, N. Ashraf, I. Vermeulen, R. F. L. de Sterke, J. C. Vlothuizen, W. J. Schouten, R. N. Almudever, C. G. DiCarlo, L. Bertels, K. Delft Univ Technol QuTech Quantum & Comp Engn Dept Delft Netherlands Delft Univ Technol QuTech Fac Appl Sci Delft Netherlands Delft Univ Technol QuTech Fac Appl Phys Delft Netherlands Delft Univ Technol QuTech Delft Netherlands Top Embedded Syst FPGA Design Best Netherlands Netherlands Org Appl Sci Res QuTech Radar Technol Dept The Hague Netherlands Delft Univ Technol QuTech Dept Quantum Nanosci Delft Netherlands

This article proposes a quantum microarchitecture, QuMA. Flexible programmability of a quantum processor is achieved by multilevel instructions decoding, abstracting analog control into digital control, and translating instruction execution with non-deterministic timing into event trigger with precise timing. QuMA is validated by several single-qubit experiments on a superconducting qubit.

关键词： Digital Control instruction Sets Quantum Computing Superconducting Processor Circuits Superconducting Quantum Processor Quantum Microarchitecture Qu MA Flexible Programmability Analog Control Digital Control instruction execution Nondeterministic Timing Event Trigger Superconducting Qubit Multilevel instructions Decoding Single Qubit Experiments Decoding Quantum Computing Computer Architecture Digital Control Process Control Coprocessors Pulse Measurements Microarchitecture Emerging Technologies Quantum Computing Hardware

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The IBM eServer z990 microprocessor

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IBM JOURNAL OF RESEARCH AND DEVELOPMENT 2004年第3-4期48卷 295-309页

作者： Slegel, TJ Pfeffer, E Magee, JA IBM Syst & Technol Grp Poughkeepsie NY 12601 USA IBM Deutschland Entwicklung GmbH IBM Syst & Technol Grp D-71032 Boblingen Germany

The IBM eServer(TM) z990 microprocessor implements many features designed to give excellent performance on both newer and traditional mainframe applications. These features include a new superscalar instruction execution pipeline, high-bandwidth caches, a huge secondary translation-lookaside buffer (TLB), and an onboard cryptographic coprocessor. The microprocessor maintains zSeries(R) leadership in RAS (reliability, availability, serviceability) capabilities that include state-of-the-art error detection and recovery.

关键词： .TLBs processor design instruction execution complex instructions Technology Group cryptographic coprocessor Architecture instruction

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The Mips R10000 superscalar microprocessor

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IEEE MICRO 1996年第2期16卷 28-40页

作者： Yeager, KC Silicon Graphics Inc. USA

The Mips R10000 is a dynamic, superscalar microprocessor that implements the 64-bit Mips 4 instruction set architecture. It fetches and decodes four instructions per cycle and dynamically issues them to five fully-pipelined, low-latency execution units. instructions can be fetched and executed speculatively beyond branches. instructions graduate in order upon completion. Although execution is out of order, the processor still provides sequential memory consistency and precise exception handling. The R10000 is designed for high performance, even in large, real-world applications with poor memory locality. With speculative execution, it calculates memory addresses and initiates cache refills early. Its hierarchical, nonblocking memory system helps hide memory latency with two levels of set-associative, write-back caches

关键词： Microprocessors Superscalar Mips R 10000 Cache Memory instruction execution

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Using a software-defined computer in teaching the basics of computer architecture and operation

Using a software-defined computer in teaching the basics of ...

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Conference on Photonics Applications in Astronomy, Communications, Industry, and High Energy Physics Experiments

作者： Kosowska, Julia Mazur, Grzegorz Warsaw Univ Technol Inst Comp Sci Nowowiejska 15-19 PL-00665 Warsaw Poland

ISBN: (数字)9781510613553

ISBN: (纸本)9781510613553;9781510613546

The paper describes the concept and implementation of SDC_One software-defined computer designed for experimental and didactic purposes. Equipped with extensive hardware monitoring mechanisms, the device enables the students to monitor the computer's operation on bus transfer cycle or instruction cycle basis, providing the practical illustration of basic aspects of computer's operation. In the paper, we describe the hardware monitoring capabilities of SDC_One and some scenarios of using it in teaching the basics of computer architecture and microprocessor operation.

关键词： software-defined computer real-time embedded system microprocessor bus protocol instruction cycle instruction execution

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A Time-Aware Code execution Continuous Monitoring for Safety-Critical Applications 6

A Time-Aware Code Execution Continuous Monitoring for Safety...

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6th International Conference on Modern Circuits and Systems Technologies (MOCAST)

作者： Chioktour, Vasileios Kakarountas, Athanasios Univ Thessaly Comp Sci & Biomed Informat Lamia Greece

ISBN: (纸本)9781509043866

The introduction of novel safety-critical applications in our day-to-day life, have increased significantly the requirement of developing systems that embed sophisticated mechanisms to ensure safe operation. The most challenging task is continuous monitoring to detect erroneous operation. The introduction of new safety standards has urged the need for novel design approaches towards safety operation. In this paper, a new technique to achieve continuous monitoring of code execution is proposed, ensuring both spatial (in terms of memory) and temporal constraints.

关键词： safety self-checking instruction execution processor continuous monitoring

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Out-of-Order Retirement of instructions in Sequentially Consistent Multiprocessors

Out-of-Order Retirement of Instructions in Sequentially Cons...

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IEEE International Conference on Computer Design

作者： Ubal, R. Sahuquillo, J. Petit, S. Lopez, P. Kaeli, D. Univ Politecn Valencia Dept Comp Engn DISCA E-46071 Valencia Spain Northeastern Univ Elect & Comp Engn Dept Boston MA USA

ISBN: (纸本)9781424489350

Out-of-order retirement of instructions has been shown to be an effective technique to increase the number of in-flight instructions. This form of runtime scheduling can reduce pipeline stalls caused by head-of-line blocking effects in the reorder buffer (ROB). Wide instruction windows are very beneficial to multiprocessors that implement a strict memory model, especially when both loads and stores encounter long latencies due to cache misses, and whose stalls must be overlapped with instruction execution to overcome the memory gap. In this paper, the Validation Buffer (VB) multiprocessor architecture is proposed as a cost-effective, checkpoint-free, scalable approach to retire instructions out of program order, while still enforcing sequential consistency, and without impacting the memory hierarchy or interconnect. Experimental results show that utilizing the Validation Buffer can speed up both release and sequentially consistent in-order retirement in future multiprocessor systems by between 3% and 20%, depending on the ROB size.

关键词： buffer storage head of line blocking effect inflight instruction instruction execution instruction sets memory architecture memory gap multiprocessing systems multiprocessor architecture out of order retirement pipeline stall processor scheduling reorder buffer runtime scheduling sequentially consistent multiprocessor strict memory model validation buffer

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Analytical-based high-level simulation of the microthreaded many-core architectures

Analytical-based high-level simulation of the microthreaded ...

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22nd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP)

作者： Uddin, Irfan Poss, Raphael Jesshope, Chris Univ Amsterdam Inst Informat Comp Syst Architecture Grp NL-1098 XH Amsterdam Netherlands

ISBN: (纸本)9781479927289

High-level simulation is becoming commonly used for design space exploration of many-core systems. We have been working on high-level simulation techniques for the microthreaded many-core architecture at the University of Amsterdam. In previous work different levels of high-level simulation for instruction execution have been proposed, where the objective of every level is to keep the highest possible abstraction in order to achieve the least complexity and highest simulation speed with a compromise on the amount of accuracy. In this article we propose a new breakthrough in abstraction by simulating entire components in applications using analytical models. This simulation technique greatly reduces the complexity of the simulator and increases the simulation speed by orders of magnitude compared to the other levels of the high-level simulator, without affecting the simulation accuracy.

关键词： multiprocessing systems University of Amsterdam analytical-based high-level simulation design space exploration instruction execution microthreaded manycore architectures Analytical models Computational modeling Computer architecture Concurrent computing Load modeling Microgrids Throughput High-level simulations many-core systems and component abstraction

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Realizing Parallelism in Quantum MISD Architecture 19

Realizing Parallelism in Quantum MISD Architecture

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16th ACM International Conference on Computing Frontiers (CF)

作者： Batabyal, Suvadip Sarkar, Kounteya BITS Pilani Dept Comp Sci & Informat Syst Hyderabad Campus Pilani Rajasthan India

ISBN: (纸本)9781450366854

We propose an idea to speed up instruction execution through a probabilistic approach, using the parallelism offered by quantum computers. For this, we divide the instruction set of an arbitrary quantum instruction set architecture (QISA) into separate groups and then bias certain qubits representing the group so that only the instructions within the group have a high probability of getting executed in a quantum processor. Therefore, the result generated will be the superimposition of the qubits as if all the instructions within the group were executed simultaneously. We show that we can achieve a significant design improvement compared to classical computer.

关键词： Quantum Computing instruction execution Quantum Architecture MISD

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