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Architectural and compiler support for effective instruction prefetching: A cooperative approach

ACM TRANSACTIONS ON COMPUTER SYSTEMS 2001年第1期19卷 71-109页

作者： Luk, CK Mowry, TC Compaq Comp Corp Alpha Dev Grp Shrewsbury MA 01545 USA Carnegie Mellon Univ Dept Comp Sci Pittsburgh PA 15213 USA

instruction cache miss latency is becoming an increasingly important performance bottleneck, especially for commercial applications. Although instruction prefetching is an attractive technique for tolerating this latency, we find that existing prefetching schemes are insufficient for modern superscalar processors, since they fail to issue prefetches early enough (particularly for nonsequential accesses). To overcome these limitations, we propose a new instruction prefetching technique whereby the hardware and software cooperate to hide the latency as follows. The hardware performs aggressive sequential prefetching combined with a novel prefetch filtering mechanism to allow it to get far ahead without polluting the cache. To hide the latency of nonsequential accesses, we propose and implement a novel compiler algorithm which automatically inserts instruction-prefetch instructions into the executable to prefetch the targets of control transfers far enough in advance. Our experimental results demonstrate that this new approach hides 50% or more of the latency remaining with the best previous techniques, while at the same time reduces the number of useless prefetches by a factor of six. We find that both the prefetch filtering and compiler-inserted prefetching components of our design are essential and complementary, and that the compiler can limit the code expansion to only 9% on average. In addition, we show that the performance of our technique can be further increased by using profiling information to help reduce cache conflicts and unnecessary prefetches. From an architectural perspective, these performance advantages are sustained over a range of common miss latencies and bandwidth. Finally, our technique is cost effective as well, since it delivers performance comparable to (or even better than) that of larger caches, but requires a much smaller hardware budget.

关键词： performance design experimentation instruction prefetching compiler optimization

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Methods to improve performance of instruction prefetching through balanced improvement of two primary performance factors

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JOURNAL OF SYSTEMS ARCHITECTURE 1998年第9-10期44卷 755-772页

作者： Park, GH Kwon, OY Han, TD Kim, SD Yang, SB Yonsei Univ Dept Comp Sci Parallel Proc Syst Lab Seodaemun Ku Seoul 120749 South Korea Syst Engn Res Inst SERI Taejon South Korea

The performance of conventional instruction prefetching mechanisms (IPMs) is analyzed in this paper based on two performance factors, i.e., the cache miss ratio and the average access time for successfully prefetched blocks. Although significant performance improvement (PI) can be obtained by improving these two factors, most conventional prefetching mechanisms improve only one factor out of these two factors. Fetching multiple blocks for a prefetch request and prefetching the sequentially next block together with the block that causes a cache miss in lookahead prefetching (LP) are proposed to improve both these factors. A new method to initiate a prefetch request earlier with no degradation of the prefetch accuracy is also presented for a memory system that is constructed as an interleaved memory. Performance evaluation is carried out through trace-driven simulation and the proposed prefetch scheme reduces 45-63% of the memory access delay time (MADT) for the cache system that does not perform any prefetching.

关键词： instruction prefetching Cache performance model with prefetching instruction cache trace-driven simulation performance analysis

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A Hybrid instruction prefetching Mechanism for Ultra Low-Power Multicore Clusters

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IEEE EMBEDDED SYSTEMS LETTERS 2017年第4期9卷 125-128页

作者： Payami, Maryam Azarkhish, Erfan Loi, Igor Benini, Luca Univ Bologna Dept Elect Elect & Informat Engn I-40136 Bologna Italy Swiss Fed Inst Technol Zurich Dept Informat Technol & Elect Engn CH-8092 Zurich Switzerland

The instruction memory hierarchy plays a critical role in performance and energy efficiency of ultralow-power (ULP) processors for the Internet-of-Things (IoT) end-nodes. This is mainly due to the extremely tight power envelope and area budgets, which imply small instruction-caches (I-Cache) operating at very low supply voltages (near-threshold). The challenge is aggravated by the fact that multiple processors, fetching in parallel, require plenty of bandwidth from the I-Caches. In this letter, we propose a low-cost and energy efficient hybrid instruction-prefetching mechanism to be integrated with a ULP multicore cluster. We study its performance for a wide range of IoT applications, from cryptography to computer vision, and show that it can effectively improve the hit-rate of almost all of them to above 95% (average performance improvement of over 2x). In addition, we designed our prefetcher and integrated it in a 4-cores cluster in 28 nm fully-depleted silicon-on-insulator (FDSOI) technology. We show that system's power consumption increases only by about 11% and silicon area by less than 1%. Altogether, a total energy reduction of 1.9x is achieved, thanks to more than 2x performance improvement, enabling a significantly longer battery life.

关键词： Energy efficiency instruction cache instruction prefetching ultralow-power (ULP) embedded multicores

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Rebasing instruction prefetching: An Industry Perspective

IEEE COMPUTER ARCHITECTURE LETTERS

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IEEE COMPUTER ARCHITECTURE LETTERS 2020年第2期19卷 147-150页

作者： Ishii, Yasuo Lee, Jaekyu Nathella, Krishnendra Sunwoo, Dam Arm Austin TX 78735 USA

instruction prefetching can play a pivotal role in improving the performance of workloads with large instruction footprints and frequent, costly frontend stalls. In particular, Fetch Directed prefetching (FDP) is an effective technique to mitigate frontend stalls since it leverages existing branch prediction resources in a processor and incurs very little hardware overhead. Modern processors have been trending towards provisioning more frontend resources, and this bodes well for FDP as it requires these resources to be effective. However, recent academic research has been using outdated and less than optimal frontend baselines that employ smaller structures, which may result in misleading outcomes. In this letter, we present a detailed FDP microarchitecture and evaluate two improvements, better branch history management and post-fetch correction. We believe that our FDP-based frontend design can serve as a new reference baseline for instruction prefetching research to bridge the gap between academia and industry.

关键词： Industries Microarchitecture prefetching Hardware History instruction prefetching branch predictor

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Execution history guided instruction prefetching

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JOURNAL OF SUPERCOMPUTING 2004年第2期27卷 129-147页

作者： Zhang, Y Haga, S Barua, R Univ Maryland Dept Elect & Comp Engn College Pk MD 20742 USA Actuate Corp San Francisco CA 94080 USA

The increasing gap in performance between processors and main memory has made effective instructions prefetching techniques more important than ever. A major deficiency of existing prefetching methods is that most of them require an extra port to I-cache. A recent study by Rivers et al. [ 19] shows that this factor alone explains why most modern microprocessors do not use such hardware-based I-cache prefetch schemes. The contribution of this paper is two-fold. First, we present a method that does not require an extra port to I-cache. Second, the performance improvement for our method is greater than the best competing method BHGP [ 23] even disregarding the improvement from not having an extra port. The three key features of our method that prevent the above deficiencies are as follows. First, late prefetching is prevented by correlating misses to dynamically preceding instructions. For example, if the I-cache miss latency is 12 cycles, then the instruction that was fetched 12 cycles prior to the miss is used as the prefetch trigger. Second, the miss history table is kept to a reasonable size by grouping contiguous cache misses together and associated them with one preceding instruction, and therefore, one table entry. Third, the extra I-cache port is avoided through efficient prefetch filtering methods. Experiments show that for our benchmarks, chosen for their poor I-cache performance, an average improvement of 9.2% in runtime is achieved versus the BHGP methods [ 23], while the hardware cost is also reduced. The improvement will be greater if the runtime impact of avoiding an extra port is considered. When compared to the original machine without prefetching, our method improves performance by about 35% for our benchmarks.

关键词： instruction prefetching instruction cache memory latency hardware prefetching

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Using basic block based instruction prefetching to optimize WCET analysis for real-time applications

Using basic block based instruction prefetching to optimize ...

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13th International Conference on Parallel and Distributed Computing, Applications, and Technologies (PDCAT)

作者： Ni, Fan Long, Xiang Wan, Han Gao, Xiaopeng Beihang Univ Sch Comp Sci & Technol Beijing 100191 Peoples R China

ISBN: (纸本)9780769548791

Cache is an important component existing in modern computer system to bridge the performance gap between the fast CPU and the slow memory system. A variety of cache optimization technologies and mechanisms are proposed to improve the cache performance, such as instruction cache prefetching. Most instruction prefetching mechanisms existing are proposed to improve the average-case cache performance. However, real-time systems care more about the worst-case performance, and the worst-case execution time (WCET) analysis of real-time applications is critical for schedulability analysis of real-time systems. Due to its unpredictable behaviour, cache disastrously complicates the WCET analysis of real-time applications. In this paper, we proposed a basic block based instruction prefetching (BBIP) mechanism to improve both the average-case cache performance and the tightness of the WCET analysis of real-time applications. Measurements on typical real-time benchmarks show that BBIP can not only eliminate most of the instruction access misses, but also result in lower WCET estimations. To discuss the effectiveness of BBIP, we measured the WCET of the benchmarks for three processor configurations with and without BBIP: 1) processor with in-order pipeline and perfect branch prediction;2) processor with out-of-order pipeline and perfect branch prediction;and 3) processor with out-of-order pipeline and 2-level branch prediction. The results show that BBIP can provide notable improvements in the tightness of WCET estimation, with the WCET values being 30.4% to 97.7% of the original ones. Our simulation results also reveal that 70% to 80% instruction access misses are eliminated with BBIP.

关键词： WCET instruction prefetching real-time basic block

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Composite instruction prefetching 40

Composite Instruction Prefetching

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IEEE 40th International Conference on Computer Design (ICCD)

作者： Chacon, Gino Garza, Elba Jimborean, Alexandra Ros, Alberto Gratz, Paul, V Jimenez, Daniel A. Mirbagher-Ajorpaz, Samira Texas A&M Univ Dept Elect & Comp Engn College Stn TX 77843 USA Texas A&M Univ Dept Comp Sci & Engn College Stn TX 77843 USA Univ Murcia Comp Engn Dept Murcia Spain Univ Washington Paul G Allen Sch Comp Sci Seattle WA 98195 USA North Carolina State Univ Dept Elect & Comp Engn Raleigh NC USA

ISBN: (数字)9781665461863

ISBN: (纸本)9781665461863

prefetching is a pivotal mechanism for effectively masking latencies due to the processor/memory performance gap. instruction prefetchers prevent costly instruction fetch stalls by requesting blocks of instruction memory in advance of their use to keep the pipeline front-end busy. the rapidly increasing instruction footprints of modern workloads have amplified the importance of such research. We propose a framework to leverage the complementary prefetching behaviors of existing prefetching techniques to create composite prefetchers. We show that recently proposed instruction prefetching techniques leverage different mechanisms from one another and find that in many cases, different prefetchers are complementary to each other. Composite prefetching allows for higher performance at lower storage overheads by combining the coverage of different complex prefetchers. We demonstrate a framework for selecting and combining state-of-the-art complex prefetchers, in a "plug-and-play" fashion, to identify the best performing combinations at various hardware overheads. We show that for every storage capacity constraint analyzed, composite prefetching outperforms prior prefetching schemes with greater improvements shown at smaller capacity constraints.

关键词： instruction prefetching hardware prefetching first-level caches datacenter applications

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Re-establishing Fetch-Directed instruction prefetching: An Industry Perspective

Re-establishing Fetch-Directed Instruction Prefetching: An I...

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IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)

作者： Ishii, Yasuo Lee, Jaekyu Nathella, Krishnendra Sunwoo, Dam Arm Austin TX 78735 USA

ISBN: (纸本)9781728186436

instruction prefetching can play a pivotal role in improving the performance of workloads with large instruction footprints and frequent, costly frontend stalls. In particular, Fetch Directed prefetching (FDP) is an effective technique to mitigate frontend stalls since it leverages existing branch prediction resources in a processor and incurs very little hardware overhead. Modern processors have been trending towards provisioning more frontend resources, which bodes well for FDP as it requires these resources to be effective. However, recent academic research has been using outdated and less than optimal frontend baselines that employ smaller structures, resulting in equivocal outcomes. This paper presents a detailed FDP microarchitecture and evaluates two improvements, better branch history management and post-fetch correction. Our mechanism provides a 41.0% speedup over the baseline (no prefetching, no FDP) with only 195 bytes of hardware overhead and outperforms the 1st instruction prefetching Championship (IPC-1) winners that had a 128KB storage budget. We believe that our FDP-based frontend design can serve as a new reference baseline for instruction prefetching research to bridge the gap between academia and industry.

关键词： instruction prefetching branch prediction

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UDP: Utility-Driven Fetch Directed instruction prefetching 51

UDP: Utility-Driven Fetch Directed Instruction Prefetching

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ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA)

作者： Oh, Surim Xu, Mingsheng Khan, Tanvir Ahmed Kasikci, Baris Litz, Heiner Univ Calif Santa Cruz Santa Cruz CA 95064 USA Columbia Univ New York NY USA Univ Washington Seattle WA 98195 USA

ISBN: (纸本)9798350326598;9798350326581

Datacenter applications exhibit large instruction footprints causing significant instruction cache misses and, as a result, frontend stalls. To address this issue, instruction prefetching mechanisms have been proposed, including state-of-the-art techniques such as fetch-directed instruction prefetching. However, our study shows that existing implementations still fall far short of an ideal system with a perfect instruction cache. In particular, up to 588.47% of potential IPC speedup of existing processors hides due to frontend stalls, and these frontend stalls are due to inaccurate and untimely instruction prefetches. We quantify the impact of these individual effects, observing that applications exhibit different characteristics that call for adaptive application-specific optimizations. Based on these insights, we propose two novel mechanisms, UDP and UFTQ, to improve the accuracy of FDIP without negatively affecting timeliness while leveraging prefetches on the wrong path. We evaluate our technique on 10 data center workloads showing a maximal IPC improvement of 16.1% and an average IPC improvement of 3.6%. Our techniques only introduce moderate hardware modifications and a storage cost of 8KB.

关键词： instruction prefetching frontend stalls data center

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Energy Consumption Analysis of instruction Cache prefetching Methods 35

Energy Consumption Analysis of Instruction Cache Prefetching...

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35th IEEE International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)

作者： Baradaran, Morteza Ansari, Ali Sadrosadati, Mohammad Sarbazi-Azad, Hamid Univ Virginia Dept Comp Sci Charlottesville VA 22903 USA Sharif Univ Technol Dept Comp Engn Tehran Iran

ISBN: (纸本)9798350381603

Frequent instruction cache (L1-I) misses pose a significant performance bottleneck in modern processors, especially for applications with large instruction footprints, such as server applications. To address the L1-I misses, there have been various proposals for L1-I prefetching over the past two decades. The designers of L1-I prefetchers primarily focused on enhancing performance while minimizing the area overhead. However, they paid little attention to the resulting increase in energy consumption due to incorporating an L1-I prefetcher. Furthermore, prior works assume L1-I prefetcher's energy consumption is mainly due to its area overhead. In this work, we demonstrate that a substantial proportion of the energy consumption associated with using an L1-I prefetcher is attributed to the increased L1-I accesses initiated by the L1-I prefetcher. To compensate for the energy consumption of more accesses to the L1-I, we propose an approach to decrease energy per access to the L1-I by reducing its associativity. Our experimental results demonstrate that reducing L1-I associativity from 8 to 2 effectively reduces the energy consumption of L1I prefetchers. As a result, the energy saving achieved through our approach (on average 113.7 nJ/ki) compensates for the energy consumption overhead caused by the L1-I prefetcher on the baseline system, with the average and the highest energy overhead at 41.6 nJ/ki and 74.8 nJ/ki, respectively, while the associated performance loss (0.8% on average) remains negligible.

关键词： energy consumption instruction prefetching instruction cache cache associativity

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